Platform Designer BFM simulation

[Aswinkrishnan]

Hi

I have been learning FPGA development for past few months. Now I have started using platform designer. I could generate an IP, do all the connections and generate HDL in VHDL.  When I tried running a BFM simulation using Questa, the files got compiled successfully without errors and warnings. But when I run the simulation on the test bench, it shows warnings that the components in top level entity are not bound. I can't proceed further and what should I do to resolve these issues.

Moreover, are their good resources, libraries or exercises about platform designer and bus functional model simulation.

Looking for a solution for these problems.

Kind Regards

Aswin

[ShengN_Intel]

Hi @Aswinkrishnan ,

Document below shows the steps related to bus functional model simulation:

https://www.intel.com/content/www/us/en/docs/programmable/683439/20-4/avalon-st-verilog-hdl-testbench.html

Click this link to download the testbench Avalon Verification IP Suite Design Files.

Design store:

https://www.intel.com/content/www/us/en/design-example/714486/cyclone-10-lp-avalon-verification-ip-suite-single-avalon-mm-master-and-slave-pair.html

https://www.intel.com/content/www/us/en/design-example/714488/cyclone-10-lp-avalon-verification-ip-suite-two-avalon-mm-master-and-slave-pair.html 

Course video:

https://learning.intel.com/Developer/learn/course/97/Avalon%2520Verification%2520Suite

https://learning.intel.com/Developer/learn/course/95/Advanced%2520System%2520Design%2520Using%2520Platform%2520Designer%253A%2520Component%2520%2526%2520System%2520Simulation

Below attached the tested BFM simulation file for your refence (check image):

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[Aswinkrishnan]

Thank you for providing links to the resources page. But I can't access it because it is due to system time out or privacy restrictions. I tried changing my system to Eastern Time, yet forbidden. I was told to contact the administrator.

[ShengN_Intel]

Hi,

Most likely you have to get an account at Intel official website https://www.intel.com/content/www/us/en/homepage.html first in order to access those links.

Thanks,

Best Regards,

Sheng

[Aswinkrishnan]

I had created the account and is logged in, but the problem still persists.

[ShengN_Intel]

Hi,

Document below shows the steps related to bus functional model simulation:

Intel website search for - Avalon Verification IP Suite: User Guide -> 18. Avalon-ST Verilog HDL Testbench

Design store:

Intel website search for - FPGA Design Store | Intel then click in and search for

1. Cyclone 10 LP - Avalon Verification IP Suite(Single Avalon-MM Master and Slave Pair)
2. Cyclone 10 LP - Avalon Verification IP Suite(Two Avalon-MM Master and Slave Pair)

Course video:

Intel website go to DEVELOPERS -> Learn -> Intel® Quartus® Prime Software: Foundation -> Home and search for

1. Avalon Verification Suite
2. Advanced System Design Using Platform Designer: Component & System Simulation

Thanks,

Best Regards,

Sheng

[Aswinkrishnan]

Thank you for that. I have been trying out that zip files and in that I was mainly understanding avlmm_2x2_vhdl. When I tried to run the simulation on the test bench in Questa, the warnings shown are

1. component instance "dut : avlmm_avls_2x2" is not bound.

2. component instance "tp : test program is not bound.

There is no simulation running. Are these errors due to libraries or something else?

For your reference, I am using Quartus prime standard 21.1 version.

[ShengN_Intel]

Hi,

I'm able to run the BFM simulation of avlmm_2x2_vhdl with Questa Starter Edition check image:

The files are attached for your reference.

Seems like your Questa needs proper license. May be you can try with modelsim and see whether the problem persists? If there is no problem with modelsim then that'll be Questa license issue. If so, you may open a new thread at Intel® FPGA Software Installation & Licensing forum.

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[ShengN_Intel · Accepted solution]

Hi @Aswinkrishnan ,

One more thing is have you follow the BFM simulation steps of avlmm_2x2_vhdl in the screenshots below?:

Best regards,
Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[Aswinkrishnan]

Hi

Thanking you for all the answers now. The program seems to be working perfectly.

I was going through the test program to understand the format and the commands that are being used to communicate with the bus. The questions I have are

1. Are those commands in the test program global? that is it could be used for writing any other simulation models?

2. Are there any pdf or resources that lists all the commands, writing a bus functional model test bench?

To understand the concept of BFM in whole, I was looking for simulating a counter module. I could use it as the slave device and control it using the master. Hence, does the test program can be used as a reference for any further examples.

Regards

Aswin

[ShengN_Intel]

Hi,

Any further update or consideration on this thread?

Let me know if you have any further concern.

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.