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Platform Designer Components and terp file format

RFris4
Novice
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I want to create a component with a variable number of Avalon-ST sinks and sources. I've been looking at the Avalon ST multiplexer _hw.tcl file as an example of how to do this and noticed that it creates the custom System Verilog file by modifying a template .terp file. This .terp file consists of TCL-like variables (e.g. $variable) embedded in the template code.

Procedures in the _hw.tcl file set variables based on the user input and then call altera_terp to (presumably) generate the customised (in this case .sv) file.

Is there any documentation for altera_terp? While it would of course be possible for each user to implement similar functionality by writing their own TCL procedures, it would be much more user friendly and an efficient use of human labour if Intel would provide documentation on how altera_terp works so that users don't have to reinvent this wheel or figure out the syntax by looking at how it is used by Intel provided IP.

 

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sstrell
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RFris4
Novice
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I must be misunderstanding something then. Let's say I want to create a component that has parameter configurable number of Avalon ST sinks, between 1 and 4.

What does the HDL contain for this component? Do I create it with the signals for all 4 Avalon ST sink interfaces and have a parameter than tells PD (and the HDL) which ports are actually active?

An example of the HDL and the _hw.tcl file showing how to do this would be very helpful!

I believe this would be something worth including in a future edition of the PD user guide.

 

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wchiah
Employee
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Hi,


You can refer for the below link

https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/defining-hdl-parameters-in-hw-tcl.html


We do a sample of _hw.tcl but for specific use, you may need to redefine the parameter based on your design.


Regards,

Wincent_Intel



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RFris4
Novice
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Thank you Wincent_Intel for taking the time to respond to my question. Unfortunately the link you provided does not provide the information I need to know to achieve what I want. Please bare in mind that I have read the documentation for PD before posting my question here, so it is unlikely that posting a link to the documentation is going to be of use.

To reiterate what I need help with:

I want to create a component that has parameter configurable number of Avalon ST sinks, between 1 and 4.

What does the HDL contain for this component? Do I create it with the signals for all 4 Avalon ST sink interfaces and have a parameter than tells PD (and the HDL) which ports are actually active?

An example of the relevant sections of the HDL and the _hw.tcl files showing how to do this would be very helpful!

 

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sstrell
Honored Contributor III
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You would need generate commands in your HDL that can implement the interfaces based on a parameter.  You would also need to create an elaboration callback in the _hw.tcl to implement the interface signaling appropriately based on the parameter.

https://www.intel.com/content/www/us/en/docs/programmable/683609/23-2/control-interfaces-dynamically-with.html

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wchiah
Employee
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Hi,

 

I wish to follow up with you about this case, did you get the answer ?

or you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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wchiah
Employee
1,624 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

 

Regards,

Wincent_Intel


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