Dear Sir/Madam,
I am currently dealing with the following issue in Quartus Prime Pro Edition 21.1, with FPGA device Cyclone10 GX:
The Quartus project contains a Platform Designer system. Inside this system there is an AXI bridge. The slave port of this bridge is exported to be connected to an external AXI4 master, and the master port is connected directly to the Avalon-MM slave port of an External Memory Interface Intel Cyclone 10 FPGA IP. The direct connection between AXI4-MM master and Avalon-MM slave translates into a Platform Designer Interconnect which converts between the two protocols.
After the Quartus project is implemented, It can be checked in the resource usage summary that in the Avalon side/agent of the interconnect there is a ..._rdata_fifo which width is 258, what makes sense because the data width selected is 256, but the depth is 8192, what translates into this fifo consuming 129 M20Ks, that is the 50% of the total available in the device. From where does this big number for the fifo depth come from? How could the resource usage of this fifo be reduced to an acceptable number?
Thanks very much in advance for your help.
Best Regards,
Eduardo del Castillo.
