Platform Designer Nios HDL generation

[Subhabrata]

I have created NIOS II based system in Platform Designer (Quartus Prime Lite 18.1). completed all connection, memory mapping and IRQ. 

But to generate HDL (Generate -> generate HDL), I am getting only .v and .sv file as output, though I have selected VHDL as HDL source. 

[sstrell]

Where are you seeing these files?  When you select VHDL, top-level files for connecting to the rest of your Quartus project should be VHDL.  Some lower-level files that you don't interact with may be Verilog.  Is that what you are referring to?  If not, what files are Verilog that you think should be VHDL?

[Subhabrata]

Hi @sstrell I am getting .v & .sv file in generated HDL folder ([folder same name as Qsys project]->synthesis->submodules). Top level component and all subcomponents also generated as verilog/sv file (instead of selecting VHDL ).

[KellyJialin_Goh]

Hi,

Greetings and welcome to Intel's forum.

Yes correct, the generated files are in .v format after you generate HDL for your simulation files.

The difference between a .v and .vhd file is <your_system>.v and <your_ip>.vhd

Here is the list of generated files from Quartus Platform Designer for your reference: https://www.intel.com/content/www/us/en/docs/programmable/683609/22-3/files-generated-for-systems.html

Hope this clarifies your doubts.

Thank you.

Regards,

Kelly Jialin, GOH

[Subhabrata]

Hi @KellyJialin_Goh  I am getting  .v and .sv file for synthesis hdl. I didn't select simulation option. Though I have selected "VHDL" in HDL file option, It is generating .v/.sv([folder same name as Qsys project]->synthesis->submodules).

Please let me know, If I missing something

Thanks,

Subhabrata

[KellyJialin_Goh]

Hi,

Any updates from your end whether the feedback provided was useful?

Hope this clarifies your doubts.

Thank you.

Regards,

Kelly

[robinr]

If i got this correct (can someone verify?) when i talked with people from mathworks, there is no problem with mixed verilog and vhdl when creating a design and programing your target with, but it can (could?) be a problem when doing simulation. And people working on fixing that solution just happend to generate verilog code from simulink and it just became the way for solving the problem, and it has become a sort of non-problem. but i asked them this very question when i met them during my education.

[RichardTanSY_Intel · Accepted solution]

If you look into the project directory -> ip -> {example_ip_name} -> synth folder, that's where the top level vhdl file generated for that particular IP, used in your qsys system.

example file path: .../<project directory>/ip/<example_ip_name>/synth

You can find it at the top level qsys synth folder as well, go to project directory -> {top_qsys_name} -> synth.

example file path: .../<project directory>/<top_qsys>/synth

The other generated file with sub-system component are usually generated in .v or .sv files format.

example file path with sub-system/ip:

.../<project directory>/ip/<example_ip_name>/<sub-system>/synth

.../<project directory>/<top_qsys>/<example_ip_name>/synth

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

[RichardTanSY_Intel]

Thank you for acknowledging the solution provided. I'm glad to hear that your question has been addressed.

Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan