How does signal routing work in Platform Designer(QSys)

[frank2597]

Hello,

I am developing software for the DE10 Nano board and i am new to working with Platform designer and had some questions to better my understanding. I am working with a golden reference design that's provided by Terasic for learning purposes. The project pretty much blinks 7 leds and the number of times it blinks is determined by C code from the HPS side. 

The name of the platform design file is called soc_system.qsys and within there i am making use of an ip called custom_leds_0 whose implementation is in the file called custom_leds.sv. The ports for custom_leds_0 are shown below:

module custom_leds
(
    input  logic        clk,                // clock.clk
    input  logic        reset,              // reset.reset
    // Memory mapped read/write slave interface
    input  logic        avs_s0_address,     // avs_s0.address
    input  logic        avs_s0_read,        // avs_s0.read
    input  logic        avs_s0_write,       // avs_s0.write
    output logic [31:0] avs_s0_readdata,    // avs_s0.readdata
    input  logic [31:0] avs_s0_writedata,   // avs_s0.writedata
    // The LED outputs
    output logic [7:0]  leds
);

In platform designer the inputs for custom_leds_0 are shown below:

The routing of signals is described below:

clk_0.clk -> custom_leds_0.clock

clk_0.reset -> custom_leds_0.reset

mm_bridge_0.mo -> custom_leds_0.avs_s0

fpga_only_master.master -> custom_leds_0.avs_s0

The signal that connects to the avs_s0 input is mm_bridge_0.mo and fpga_only_master.master.  The avs_s0 input into the custom_leds_0 ip is composed of several signals. The first Is an input address type which we self-defined with a bit-width of 1. What I am unsure Of is what this input is connected to. I am also not sure what the read and write inputs Are connected to either but they both also have bit-widths of 1.  I know that avs_s0 is connected to "mo" from the mm_bridge_0 ip and that its also Connected to the master from fpga_only_master ip in platform designer however it Is not clear what is explicitly  getting mapped/connected to the various input signals of the avs_s0, That’s where my confusion is. 

Can anyone help me understand the explicit  connections that are wired b/w mm_bridge_0.mo, fpga_only_master.master and custom_leds_0.avs_s0? If you want me to clear anything up in my question please let me know. Thanks

The project is 120MB which is over the limit for uploading so you can find the project files at the google drive link below:

https://drive.google.com/drive/folders/1nF_FMn7xCJBifag5QRBkbpPhO-g9yHFz?usp=sharing

[sstrell · Accepted solution]

The thing about Platform Designer is that you don't need to know any of these details.  As long as Avalon host and agent interfaces follow the Avalon standard, they can be connected together and PD will automatically build the interconnect based on these connections.

To answer your specific questions, the address signal is a single bit because there is only 1 (or maybe 2) addressable locations in this custom component.  The read and write inputs are control signals to read from or write to the custom component.

Not sure if that answers your questions.  Check out this training to learn about standard interfaces: https://cdrdv2.intel.com/v1/dl/getContent/652986

[RichardTanSY_Intel]

Thank you for acknowledging the solution provided. I'm glad to hear that your question has been addressed.

Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Best Regards,

Richard Tan