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I just created my first Qsys file with my own component and wanted to simulate this design with my own testbench file (Quartus Prime Pro 18.1). When calling "com" in msim_setup.tcl, I get an error saying:
Could not find rdma_10.test_rdma_0_rdma_10_fwzwsoq.
When looking in the generated sim-file, I see this:
...
end component test_rdma_0_rdma_10_fwzwsoq_cmp;
for rdma_0 : test_rdma_0_rdma_10_fwzwsoq_cmp
use entity rdma_10.test_rdma_0_rdma_10_fwzwsoq;
begin
rdma_0 : component test_rdma_0_rdma_10_fwzwsoq_cmp
generic map (
IMAGE_MAX_WIDTH => 1024,
IMAGE_MAX_HEIGHT => 1024,
IMAGE_PITCH => 1024,
BURST_BITS => 8
)
The same file, but in the synth-folder looks like this:
end component input_rdma_cmp;
for rdma_0 : input_rdma_cmp
use entity rdma_10.input_rdma;
begin
rdma_0 : component input_rdma_cmp
generic map (
IMAGE_MAX_WIDTH => 1024,
IMAGE_MAX_HEIGHT => 1024,
IMAGE_PITCH => 1024,
BURST_BITS => 8
)
TL;DR: Synthesis works, simulation doesn't. Simulation wants to use "rdma_10.test_rdma_0_rdma_10_fwzwsoq", but this isn't defined anywhere. It should be "rdma_10.input_rdma", like in the synthesis file.
Is there some kind of hidden feature or a bug?
Thanks in advance, Dominik
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Small update: Found a solution to the upper problem.
In the Component Editor one of my three files was marked with the attribute "Top-level file", but the "Top-level Module" field was grey. After clicking on "Analyze HDL files" the "Top-level Module" has been updated and the files have been generated correctly! I'd still say, that this is an undefined behaviour and a bug, but there seems to be a solution for this.
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Hi,
It was an issue with v16.1 pro but it has been fixed in v17.1,
will conform with v18.1pro.
Best Regards
Vikas Jathar
(This message was posted on behalf of Intel Corporation)

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