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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Platform designer Avalon Communication

Aswinkrishnan
Beginner
428 Views

Hi

I am trying to generate a simple system which consists of an Avalon MM master BFM and an Avalon memory mapped slave. My avalon slave consists of two components, having an interface to the other component. When I try to generate HDL,

1. It doesn't create ports for avalon communication. Thus, how can I control the communication?

2. Are there any testbench examples to simulate the process between master and the slave, to learn about the testing procedure?

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sstrell
Honored Contributor III
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1) Not sure what you mean here.  "Doesn't create ports"?  If you're creating a custom component (using Component Editor I presume) you create the ports and specify their function on the Signals & Interfaces tab.  Maybe more detail is needed here.

2) From the Generate menu, you should choose to generate a testbench system design for your custom component.  This will automatically configure and attach an appropriate BFM to it and create the simulation scripts you would use, but you have to write the testbench using the BFM API to control the commands sent (and monitor the responses back).  This training is a little old, but it covers the basics: https://cdrdv2.intel.com/v1/dl/getContent/653122?explicitVersion=true

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Aswinkrishnan
Beginner
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My master has the clock and reset as input ports. The output ports should be avalon slave address and etc. But the AVS ports are not visible in the ports of the HDL generated. 

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sstrell
Honored Contributor III
380 Views

Again it's still not clear what you are referring to.  Did you use the Component Editor to create a custom component and you are saying that when you add the component to a system, you are not seeing the interfaces you defined?  Maybe screenshots or more detail needed.

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ShengN_Intel
Employee
373 Views

Hi,

 

In Platform Designer, you'll able to see the output signals of Avalon Memory Mapped Slave BFM after show signals. After HDL generation, those ports also available in the .v file check the images below.

ShengN_Intel_0-1675221964445.png

ShengN_Intel_1-1675222000849.png

 

Best regards,

Sheng

 

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.

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Aswinkrishnan
Beginner
363 Views

Avalon Master has these Avalon ports as output. The Avalon slave has an Avalon slave port as input. When we generate HDL for the entire system, in the port declaration of the entity, Avalon ports can't be seen. 

In platform designer, component, show signals, Avalon signals can be seen though.

I will look into this more.

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ShengN_Intel
Employee
347 Views

Let me know if you have any further update.


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