PowePlay. I/O power and core static power

[Altera_Forum]

I'm trying to understand how PowerPlay works. 

  I use Quartus 10.1 sp1.   I have two projects (A and B) that execute exactly the same task. These projects are implemented on the same FPGA (Cyclone IV) and use the same pins (same locations).  The internal structure of the two circuits is however quite different ( B uses 15000 FF while A uses only 200 FF and some logic).   The circuits A and B are simulated at gate level with the same testbench and produce exactly the same output! The output is stored on a .vcd file both for A and B. The testbench is long enough to properly stimulate all the internal paths of the circuits A and B.   When I run the PowerPlay analyzer I get the power dissipation data. In both cases (A and B) the confidence metrics is defined as high. Below the summary of the reports.    A  Total Thermal Power Dissipation 92.66 mW  Core Dynamic Thermal Power Dissipation 4.93 mW  Core Static Thermal Power Dissipation 80.91 mW  I/O Thermal Power Dissipation 6.81 mW   B Total Thermal Power Dissipation 188.05 mW Core Dynamic Thermal Power Dissipation 85.36 mW Core Static Thermal Power Dissipation 89.14 mW I/O Thermal Power Dissipation 13.55 mW   I have two questions. 1) Since the used pins are the same and the input and output transitions are also the same, why the I/O power is so different? 2) The circuits differ largely in the dynamic power dissipation and I do expect this. However there is also a huge amount of static power dissipation. Where this static power comes from? If these are internal FPGA circuits that cannot switched off why there is a difference between A and B?     Thank you in advance for any hint.

[Altera_Forum]

Hi, i believe the static power different between project A and B might due to the different of internal structure of both project. 

Static power is mostly a function of how many transistors need to maintain their state as well as circuit design. The FPGA static power is proportional to the static current ICC, the current that flows regardless of gate switching (transistor is ON “biased” or OFF “unbiased”).

[Altera_Forum]

For the static power, my experience is when you have more logic utilization, the static power will increase. The static power is something that does not depend on toggle rate but rather the utilization. The number of FFs in B is much more than A, thus it is expected to have higher static core power in B. 

 As for the IO power, generally it should not depend on core logic utilization. Just wonder if you have a chance to look into if there is any difference in IO settings?

[Altera_Forum]

I checked the I/O settings. The only warning was on missing slew rate and drive strenght on the single output of the circuit. I explicitly set these and repeated the analysis obtaining no changes on the result. 

 Below a report that compares the I/O settings on the two circuits. I don't see any difference!    Circuit A Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment ------------------------------------------------------------------------------------------------------------- Din : M11 : input : 2.5 V : : 4 : Y  reset : J6 : input : 2.5 V : : 3A : Y  clk : J7 : input : 2.5 V : : 3A : Y  Dout : B11 : output : 2.5 V : : 7 : Y   Slew rate set to 2 and drive strength set to 16mA  Signal activities  Toggle rate (mil trans/sec) Toggle rate data source static probability static probability data source Din Input 0.031 simulation(f1) 0.557 simulation (f1) reset Input 0.001 simulation(f1) 0.000 simulation (f1) clk Input 199.999 simulation(f1) 0.5 simulation (f1) Dout Output 0.031 simulation(f1,f1) 0.407 simulation (f1,f1) Simulation (f1, f1)  *** Circuit B  Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment ------------------------------------------------------------------------------------------------------------- Din : M11 : input : 2.5 V : : 4 : Y  reset : J6 : input : 2.5 V : : 3A : Y  clk : J7 : input : 2.5 V : : 3A : Y  Dout : B11 : output : 2.5 V : : 7 : Y   Slew rate set to 2 and drive strength set to 16mA  Signal activities  Toggle rate (mil trans/sec) Toggle rate data source static probability static probability data source Din Input 0.031 simulation(f1) 0.557 simulation (f1) reset Input 0.001 simulation(f1) 0.000 simulation (f1) clk Input 200 simulation(f1) 0.5 simulation (f1) Dout Output 0.031 simulation(f1,f1) 0.407 simulation (f1,f1) Simulation (f1, f1)  I wonder if there's a formula to calculate the I/O power. It should be something like P= 0.5 * C_pin * (Vdd_pin^2)*fclk * switching_activity + Vdd_pin* I_pin_static. Are these values available somewhere?

[Altera_Forum]

Still digging into the report files. 

I found a significant difference in th power dissipated by the ignal 'clk~inputclkctrl' indicated as a clock control block.  Is there anybody that knows which is the function of this block/signal?  I'm guessing that the circuit A thahas less FF dissiates less power on the clock signal w.r.t. circuit B. Everything would be fine ifthe power dissipated by the clock would be reported in some way as I/O power. What do you think?