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Valued Contributor III
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Power consumption prediction by extrapolation

Hello everyone, 

 

I synthesized a particular design in a Cyclone IV FPGA (EP4CGX150DF27C7) and extracted the following power consumption predictions: 

Total power dissipation: 240.08mW 

Core dynamic thermal power dissipation: 34.40mW 

Core static thermal power dissipation: 119.93mW 

I/O thermal power dissipation: 85.75mW 

 

Does anyone now how I could extrapolate these information to a configuration including 20 of the previous design, without synthesizing it? 

Is there some rules to follow? 

Avoiding a synthesis will just make me save time, but maybe power consumption can't be extrapolated as resources utilization could... 

 

Thank you for your help! 

 

J-B
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Valued Contributor III

Re: Power consumption prediction by extrapolation

In this thread 

 

http://www.alteraforum.com/forum/showthread.php?t=38168&p=157327#post157327 

 

There is a file de0_nano_power.pdf 

 

This is a design where the device was filled with counters that could be selectively enabled. Several versions of the designs were tested with different counter widths. You can see from the straight lines that extrapolation of the design would have been sufficient to predict a larger design. 

 

So, yes, you can extrapolate your data. If you would like to be conservative in your power estimates, you can create a similar design to that used to test the DE0-nano - since the counters used in that design have the worst-case toggle rates (a 1-bit counter toggles on every clock). 

 

Cheers, 

Dave
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Valued Contributor III

Re: Power consumption prediction by extrapolation

 

--- Quote Start ---  

In this thread 

 

http://www.alteraforum.com/forum/showthread.php?t=38168&p=157327#post157327 

 

There is a file de0_nano_power.pdf 

 

This is a design where the device was filled with counters that could be selectively enabled. Several versions of the designs were tested with different counter widths. You can see from the straight lines that extrapolation of the design would have been sufficient to predict a larger design. 

 

So, yes, you can extrapolate your data. If you would like to be conservative in your power estimates, you can create a similar design to that used to test the DE0-nano - since the counters used in that design have the worst-case toggle rates (a 1-bit counter toggles on every clock). 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

Ok, so if I implement 20 times my initial design which consumes 240mW, I should have a power consumption of 20*240mW? It seems to be a lot but it's what I guess after your de0_nano_power.pdf scheme... 

Or is it only the core dynamic power consumption which needs to be multiplied by 20? 

 

Thanks for helping! 

 

J-B
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Highlighted
Valued Contributor III

Re: Power consumption prediction by extrapolation

 

--- Quote Start ---  

Ok, so if I implement 20 times my initial design which consumes 240mW, I should have a power consumption of 20*240mW? It seems to be a lot but it's what I guess after your de0_nano_power.pdf scheme... 

Or is it only the core dynamic power consumption which needs to be multiplied by 20? 

 

--- Quote End ---  

 

 

There are three things you would need to consider; core static power (which goes up with temperature), core dynamic power, and I/O power. 

 

If you have an evaluation kit, my advice is to run a few hardware tests with your design and a worst-case toggle design and see how much they differ. 

 

I've tried to get estimates from Quartus PowerPlay, eg., for the DE0-nano design, but the estimates do not match hardware measurements, so I have low confidence. The estimates were based on .vcd dumps from Modelsim, so they should have been accurate. The simulations for larger designs take forever, so using an evaluation kit is a more effective use of time. 

 

Cheers, 

Dave
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