Honored Contributor II
11-10-2016 12:39 AM
Hi,I am trying to instantiate 10GBASE-R Transceiver on my Stratix V GX FPGA to drive 2 SFP+ ports connected to each other via SFP cable (one transmit, one receive) and do signal quality tests on the system. I have been reading the Transceiver User Guide, looking at 10G low latency and Native PHY transceiver example designs, but I can't figure out how to instantiate all the parts and put them together via Quartus. I know that BASE-R transceivers need the PHY-IP, Reconfiguration Controller, and Reset Controller instantiated, but I can't figure out how to connect these components. Part of this stems from my limited knowledge of Quartus, FPGA designs, and verilog. I have done some free online courses from Altera to get started with Verilog, Transceiver design flow, and Quartus, but I am wondering if anyone can provide additional resources for learning these topics or helping to create a transceiver design. Thanks in advance.