I have a code
LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity REG_FILE is port ( REG_ADDR_IN : in std_logic_vector(15 downto 0); -- some code ); end REG_FILE; architecture behavior of REG_FILE is --some code signal mailbox_idx : integer := 0; process(REG_CLK) begin -- some code mailbox_idx <= to_integer(to_unsigned(REG_ADDR_IN)); end process; end behavior;And result
mailbox_idx <= to_integer(REG_ADDR_IN); Error (10405): VHDL error at reg_file.vhd(75): can't determine type of object at or near identifier "to_integer" -- found 0 possible types or this way mailbox_idx <= to_integer(to_unsigned(REG_ADDR_IN)); Error (10476): VHDL error at reg_file.vhd(75): type of identifier "REG_ADDR_IN" does not agree with its usage as "natural" type Error (10346): VHDL error at reg_file.vhd(75): formal port or parameter "SIZE" must have actual or default valueWhere is a problem?
Hi,Read function description: function TO_UNSIGNED ( ARG,SIZE: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (SIZE-1 downto 0) -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with -- the specified SIZE. As you can see you did not specify "SIZE" parameter and your REG_ADDR_IN has to be integer type also. I recomend googling about libraries and packages usage in VHDL. I usualy use just two libraries: use ieee.std_logic_1164.all; use ieee.numeric_std.all; and if you need some type conversion use: https://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/ (https://www.doulos.com/knowhow/vhdl_designers_guide/numeric_std/)
--- Quote Start --- Yes. The problem was use ieee.std_logic_arith.all; Thank you. --- Quote End --- Yes - std_logic_arith and numeric_std have the same functions and types declared, so they clash, and neither of them are visible. std_logic_arith is not a standard VHDL package (neither is std_logic_unsigned), while numeric_std is. I recommend deleting std_logic_arith.