Problem in Quartus Prime I++ HLS Compiling "The command line is too long."

[Engineer87]

hello every one.

 I got sticky problem in compiling my C++ code.

when compiling wants to be finished the compiler stops and showing this message:

The command line is too long.
HLS Main Optimizer FAILED.

Here is my command line:

 -march=Arria10 main.cpp -o test-fpga.exe

and I have uploaded Image of Error...

thanks for answers...

[BoonBengT_Intel]

Hi @Engineer87,

Thank you for posting in Intel community forum and hope all is well.

May I know what are the HLS version you are having?

And also would it be possible to share the .cpp files you have for us to simulate the issues?

Hope to hear from you soon.

Best Wishes

BB

[Engineer87]

hello 

At first thanks for your answer. yes my Quartus prime version is 17.1

my code is image processing and I share it to you...

the command line  and log is in attachment.

sincerely.

[BoonBengT_Intel]

Hi @Engineer87,

Noted on the project files as well as the error logs.

Allow us some time to check on the situation and will get back at earliest.

Thank you for the patients

Best Wishes

BB

[Engineer87]

Hello. Did you get any solution or results yet? Thnx for sharing...

[BoonBengT_Intel]

Hi @Engineer87,

Thank you for the hold, we have managed to try and compile the code provided and it compile successfully for emulator mode. (with some minor error where main.cpp include image.h instead of Image.h)

Hence there are still posibilities that it is environment or code might be the issues. So perhaps would suggest to check on the below:

- did you managed to compile the design emulator flow and successfully completed?

- did you managed to compile other more simple design from the example?

- based on the error logs there seems to be connection to math.h, however did not see it part of the import, may i know what is the connection there?

Best Wishes

BB

[Engineer87]

Hello and thnx for your answering. Fyi the design is ok with x86 architecture in i++ compiler and make .exe file correctly but in fpga mode does not work and had error as mentioned. And for your second note i should say yes i try and successfuly compiled and program cyclonev chip with counter.cpp and image down.cpp example so i think my program version  is ok . but in your third sentense you said math.h , i appreciatd that you spread it more for me... about log and what you saw in it about math.h and what should i do? Thank you for your attention and i wait for your answer. I saw other topic problem like command line is too long, and i did not found any useful solution for it. Fyi :

https://community.intel.com/t5/Intel-High-Level-Design/HLS-Main-Optimizer-Failed-The-command-line-is-too-long/td-p/707169

Please check it. I am still waiting for your solutions.

Best regards.

[BoonBengT_Intel]

Hi @Engineer87,

Thanks for the information, good to know that some example design are programmed successfully for CycloneV devices.

Follow up question, are you having issues on the Arria10 or CycloneV devices? Is it correct to say example design both successfully compiled and program on Arria10 and CycloneV and just this design are failing in both devices for hardware compilation?

The success programmed previously rules out the environment setting issues, hence we might be seeing some code or hardware issues.

Hope to hear from you soon.

Regards

BB

[Engineer87]

Hey. Thanks for your attention. Yes examples of the intel is correctly program in cyclonev or arria10. It seems the example designs are very simple and small. For example counter and ... . I think the error command is too long reffer to a buffer or for example option jn program that should be extended or some thing. What does it mean too long? Too long for what?
Thank you.

[BoonBengT_Intel]

Hi @Engineer87,

Good day, just following up on the previous clarification.

By any chances did you managed to look into it?

Hope to hear from you soon.

Best Wishes

BB

[Engineer87]

Hello and thnx for your attention. Yes, maybe cyclonev or aria10 are small for this design??? Did you know other chip i mean bigger ones? When in x86 arch it works it mean the code is correct by i++ . am i right? What is happened by the march cyclonev or aria10?

[BoonBengT_Intel]

Hi @Engineer87,

Yes with the success emulator flow, chances is the code are not the issues.

There are possibilities that design overfit, to look for other fpga with bigger resources you can find that details in the link below:

- https://ark.intel.com/content/www/us/en/ark.html

Note: Click on Intel® FPGAs and pick the required device to see their resources.

Hope that clarify

Regards

BB

[BoonBengT_Intel]

Hi @Engineer87,

Greetings, just checking in to see if there is any further doubts in regards to this matter.

Hope your doubts have been clarified.

Best Wishes

BB

[BoonBengT_Intel]

Hi @Engineer87,

Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes

BB

[Engineer87]

Hello dear. I finally found the answer. There was no solution in sites and net. and Thanx for your attention. I post the answer soon.

[Engineer87]

I do appreciate your attention and time. Thnx again.

[Engineer87 · Accepted solution]

I finally found the solution. The answer is : compiling c++ code in fpga mode with i++ compiler needs a huge amount of Ram and hdd resource for page filing. For example a cycloneV design needs about 64gb ram and resource. it depends on your design. That is it.