Where are the example files

[MATRIX7878]

Hello,

     I generated a few examples in Verilog (as VHDL was not an option) for EMIF, PCIe and a few others.  I opened up the .qsf file and I see all the IP's being used, but I cannot find a top-level file that actually gives me the code of the program I wanted.  I was expecting a .v file that shows me how to code the protocols.  Where can I find the .v files that I seek?

Thank you,

Drew

[sstrell]

I'm assuming you are generating instances of these IPs, not an "example design" which is a complete Quartus project you can use to test an IP.  I'm more familiar with EMIF, so for that IP, there should be a folder with the name you used for the instance.  All the files for the IP are in there, including the top-level file (.v from your message) so you can instantiate it.

[MATRIX7878]

Hello,

I believe so.  I am using the example design tab in the IP to generate the Verilog files (attached image).  It created a new folder called the example design.  The other attached image are all the files and folders in the IP folder.  Where is the top-level actually at?  I see some .v files, but none of them seem like code that will program the memory, or even connect to other files.

On a semi-related note, I can only get Verilog files, is VHDL not supported for EMIF?

Thank you,

Drew

[sstrell]

So you're creating the full example design, not just an IP instance.  If that's the case, there's nothing to instantiate.  You open the new example design project's .qpf file (File menu -> Open Project) in the qii directory and work from that new project.  The top-level file in the example design project is a Platform Designer system named ed_synth.qsys (example design for synthesis).  If you want an instance to instantiate instead of a full example design, click Generate HDL from the bottom of the IP Parameter Editor or from the Generate menu at the top.  This will give you a top-level file and other needed files for synthesis in the HDL you choose from the Generate HDL dialog box.

As for the HDL for the example design, you have to switch the option (HDL Selection) in your screenshot on the Example Design tab.

[MATRIX7878]

Hello,

     Alright I see.  I was creating a whole project for the device, not just the part I want.  For the Generate HDL, that does have VHDL, the generate design EXAMPLE does not.  That is only Verilog.  I do now see the instantiated top-level file.  I am hoping that the whole DDR protocol is somewhere also.  I see the instantiation file in .vhd, but do not see any other .vhd files.  Where are the other files that I will need?  I am trying to learn the protocol.

Thank you,

Drew

[sstrell]

The HDL option for the example design is right in the screenshot you attached.  First option on the Example Design tab.

What "other files" are you looking for?  It's not clear what you need at this point.  If you are saying that you want to try to understand how an EMIF works by going through the HDL for the IP, that isn't really going to help much because most of the interface is hardened.

[MATRIX7878]

Hello,

     Yes, I know that.  I opened the drop-down menu and only Verilog was there.

     I am looking for a file that explicitly does the DDR protocol.  What addresses I need to call/what mode I need to put it in, what start, stop, ACK, NACK, etc. signals I need to implement a DDR protocol.  I am looking for a program that will show me how a processor talks to the memory.  Is that not what the HDL code does?  It will only show me the components I need to implement the protocol, not the protocol itself?  Is that right?

Thank you,

Drew

[sstrell · Accepted solution]

Didn't realize that about the HDL selection.  VHDL probably coming in a future version.

The whole point of an IP is that it isolates you from these details.  All you need to do is use the programming model for the IP (either at the hardware level with register access or at the software level with macros created using software tools) to read and write the memory.  And again, since most of the interface in newer devices is hardened, the only HDL code you will see is the implementation of the Avalon or AXI connection to the hard IP.

As far as a processor is concerned, if you are talking about the HPS in an SoC device, rocketboards.org is the place to go for examples.

If you are looking at learning the details of signaling between the FPGA and the external memory, download a spec sheet from Micron or any memory manufacturer.  Very detailed explanations on how everything works.

[MATRIX7878]

Hello,

     No problem.  I hope it comes out later.

     Oh, that is what the IP is for?  Like a standard library in other languages.  I see what you are saying.

     It does not need to be processor specific, just the protocol in general.  For example, if I bought 2 different mother boards, I could use the same DDR5 memory with both.  Not at the same time of course, but I believe you know what I mean.

     I have found some datasheets for the protocol, but I have yet to find any code examples.  Reading is one thing, being able to implement it is another for me.  I'm not the best at translating plain English into code.  I need more pseudo-code.

Thank you for your help though, I understand I have more to do.

Drew

[AdzimZM_Intel]

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