Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Problem with SignalTap in QuartusII v 13.0sp1 and device EP1S40F780C7

Aaria3
Beginner
1,423 Views

I have all the time this error:

Error (261009): Cannot run SignalTap II Logic Analyzer. SignalTap II File is not compatible with the file programmed in your device. The expected compatibility checksum value is 0x2DB51B6F; the value read from your device is 0x9EDA8DBF 

 

I was checking on the forum different problems and I try all that I read and the error persist:

-Remove the DB folder/output files/ incremental compilation

-Remove the .stp file and regenerate

 

I have also found another strange behavior, when in the top level I coment some models then it works perfecly, but if not give me the same error of the checksum.

 

I have to say that the design hasn't any critical warning or warnings about the design rules...

 

Someone have experience with this problem?.

 

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2 Replies
Vicky1
Employee
201 Views

Hi,

Can you please check the below solution note & let me know how it works in this case,

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

 

Best Regards,

Vikas Jathar

Aaria3
Beginner
201 Views

Hi,

I already read this information and I use always the basic AND trigger in the SignalTap.

And there is a strange behavior because in my top level FPGA if I add some entities I get the error, but with others not.

 

Best Regards,

Alen.

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