Problem with Synthese in Quartus with Customer-IP vhdl-file

[Altera_Forum]

Hi All, 

 I make a Customer IP and when I wont make a synthese, I have following error-message:  Error (10820): Netlist error at ime_avalon_xy_detector.vhd(109): can't infer register for count_hsync[1] because its behavior depends on the edges of multiple distinct clocks   In the attachment you find the entire vhdl file. The problematic part is in the xy_coordinate : process.  In HDL-Designer and QuestaSim I could make a success simulation. But the stimuli does not affect the same as in quartus II. But I need the signal as in the simulation (the last 5 waves in pdf file). How I can make a process with multiple distinct clocks?  Thanks you...

[Altera_Forum]

Hi Antonio, 

 You use two clocks in one process (coe_iVHA_HS and coe_iVGA_CLK). Like you said that could work in simulation, but how would a hardware implementation look like?  I would make a seperate process for the flag_hs signal, which look like:  process(coe_iVGA_HS, coe_iRST_N, reset_hs_flag) begin if coe_iRST_N = '0' or reset_hs = '1' then  flag_hs <= '0'; [/INDENT] elsif(coe_iVGA_HS = '1' AND coe_iVGA_HS'event) then  flag_hs <= '1'; [/INDENT] end if; end process;  define a signal reset_hs_flag and change  line 112 to reset_hs_flag <= '0'; line 125 to reset_hs_flag <= '1';  Remove lines 116 and 117.  I dont know if coe_iVGA_HS and coe_iVGA_CLK are asynchronous. If they are, take measures for clock domain crossing.  Succes, Ton

[Altera_Forum]

yes it works well now... ;O) 

 Thanks you very much.

[Altera_Forum]

Hi std_logic_vector 

 << I dont know if coe_iVGA_HS and coe_iVGA_CLK are asynchronous. If they << are, take measures for clock domain crossing.    coe_iVGA_HS and coe_iVGA_CLK are synchronous, that are not problem...   Bye ;)