Problem with SystemVerilog operator ++ in Modelsim

[Altera_Forum]

I have some problem simulating code using the SystemVerilog ++ operator. Consider the following example (I tested this on QuartusII Web edition 9.1sp2 using ModelSim AE): 

   --- Quote Start ---   module test_sv ();   logic clk = 0;  logic [7:0] cnt1 = 0;  logic [7:0] cnt2 = 0;  logic test, next_test = 0;    always# 10ns clk = ~clk;   always @ (negedge clk) next_test <= cnt1[0] & cnt2[0];   always_ff @ (posedge clk) begin `ifdef PLUSPLUS  cnt1++; `else  cnt1 <= cnt1 + 1; `endif  end  `ifdef MOVE_CNT2  always_ff @ (posedge clk) begin `ifdef PLUSPLUS  cnt2++; `else  cnt2 <= cnt2 + 1; `endif  end `endif    always @ (posedge clk) begin  test <= cnt1[0] & cnt2[0];  # 1;  assert(test == next_test);  end  `ifndef MOVE_CNT2  always_ff @ (posedge clk) begin `ifdef PLUSPLUS  cnt2++; `else  cnt2 <= cnt2 + 1; `endif  end `endif  endmodule   --- Quote End ---  Saving this as test_sv.sv and running the following ModelSim commands:   --- Quote Start ---   vlog test_sv.sv  vsim work.test_sv run 100 ns  vlog +define+MOVE_CNT1 test_sv.sv  restart -f run 100 ns  vlog +define+PLUSPLUS test_sv.sv  restart -f run 100 ns  vlog +define+PLUSPLUS +define+MOVE_CNT1 test_sv.sv  restart -f run 100 ns   --- Quote End ---  The two first simulations work fine. They both avoid the ++ operator. The two last simulations result in errors. Actually they differ in result if you examine the waveforms.  It seams that QuartusII will synthesis the cnt1++ equivalent as cnt1 <= cnt1+1. i.e. there is a mismatch between simulation and synthesis result.  Does anybody know if there is any special considerations that must be made when using ++ operator? Should this work or am I missing something?  /Henrik

[Altera_Forum]

I think cnt1++ is 

equivalent to cnt1 = cnt1+1 and not to cnt1 <= cnt1+1  One is immediate the other is a deferred assigment.