Problem with accessing the DE1 board SRAM

[Altera_Forum]

I am having trouble reading the SRAM on the DE1 board :(. Below are the code used to access the SRAM. My objective is to write data to an address once and read that particular address more than once. The tester_clock runs at the speed of 100MHz. The picture uploaded is the block diagram for the system.  

 The pins were analysed by SignalTap. The data x"0505" seems to be transmitting to the SRAM. However, I received no responds from the SRAM.   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all;   entity sram_test is  port(   SRAM_ADDR : out std_logic_vector (17 downto 0);  SRAM_DQ : out std_logic_vector (15 downto 0);  SRAM_WE_N : out std_logic;  SRAM_OE_N : out std_logic;  SRAM_UB_N : out std_logic := '0';  SRAM_LB_N : out std_logic := '0';  SRAM_CE_N : out std_logic := '0';  tester_clock: in std_logic ); end entity;   architecture rtl of sram_test is signal in_SRAM_WE_N : std_logic := '0'; begin  process (tester_clock)-------------  begin  if (rising_edge(tester_clock)) then  if (in_SRAM_WE_N = '0') then -- Write mode  SRAM_ADDR <= (others => '0'); -- Address location 0 selected  SRAM_WE_N <= '0';  SRAM_OE_N <= '1';  SRAM_DQ <= x"0505"; -- Write data to selected address  in_SRAM_WE_N <= '1'; -- Switch to read mode   elsif (in_SRAM_WE_N = '1') then -- Read mode  SRAM_WE_N <= '1'; -- Read mode selected  SRAM_OE_N <= '0'; -- Output enabled  SRAM_ADDR <= (others => '0');   end if;   end if;  end process; end rtl;  http://www.alteraforum.com/forum/attachment.php?attachmentid=10709&stc=1

[Altera_Forum]

I am not familiar with the SRAM, but I found this example: http://pentevo.googlecode.com/svn/fpga/tests/test_dram/sram_control.v 

There the SRAM is controlled with a three cycle write. Might it be that you require the same?