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Problem with low latency 100GE IP core.


I am trying to integrate low latency 100ge IP core into my platform designer project. The device is 1SG280HU2F50E2VGS1. The core does not possess an Avalon slave memory mapped interface. There is an interface called 'status' which has all the signals for connecting to the Avalon bus but is defined as 'conduit' so it does not mate with the Avalon master. How do I connect the core to the Avalon bus? Thanks.

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Hi Zljus,


Yes, I can observe the same. The LL 100G and LL 40G is not fully ready in Platform Designer, and there should have some improvement in the further version. For now, i think we need to connect those signals manually at the top level of the design.


Best Regards -SK Lim​