Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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I am using Altera's Schematic tool for the first time and I have a simple problem. I have a big SOPC's "BDF" block and on my top level I am connecting a PLM_DFF (BSF) block to one of the big block outputs. In my simulation I have all the inputs ready at the FF but I am not getting ant output out off the FF. Any idea that what I am doing wrong! Thanks JSM
As I said in my question, Clock to the DFF is at the clock input and clearing\presetting it is at th correct signal level. I have all the inputs correctly at the FF inputs but I am not getting any output.
