- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi All,
I am using Altera's Schematic tool for the first time and I have a simple problem. I have a big SOPC's "BDF" block and on my top level I am connecting a PLM_DFF (BSF) block to one of the big block outputs. In my simulation I have all the inputs ready at the FF but I am not getting ant output out off the FF. Any idea that what I am doing wrong! Thanks JSMLink Copied
4 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Forgetting to clock the DFF? or clearing\presetting it with the wrong signal level?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
As I said in my question, Clock to the DFF is at the clock input and clearing\presetting it is at th correct signal level. I have all the inputs correctly at the FF inputs but I am not getting any output.
jsm- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
using Quartus Simulator or ModelSim?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks everyone. I resolved the issue. It was seting up the output port for the input port.
Thanks
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page