Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17267 Discussions

Problems to program Cyclone V GT FPGA

Altera_Forum
Honored Contributor II
2,621 Views

Im new using Altera boards I have two questions. 

I check the Quartus_II_Introduction for verilog users. On the programming chapter it says that "DE0-CV, DE0-Nano and DE2-115 Boards" should have a RUN/PROG switch. 

 

1.-Does the cyclone V GT FPGA board has such switch? 

2.-Also where can I find the pin assignments for this board? 

 

Thank you
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
1,716 Views

Did you notice the Cyclone V GT DevKit Reference Manual? 

 

Best way to get the pin assignments is to import a reference design shipped with the board.
0 Kudos
Altera_Forum
Honored Contributor II
1,716 Views

Hi, 

 

1.We dont have such switch but take care SW4.4 and SW5 setting for programming. 

For more information you can refer user guide https://www.altera.com/en_us/pdfs/literature/ug/ug_cvgt_fpga_dev_kit.pdf 

2.For pin related information,use reference guide https://www.altera.com/en_us/pdfs/literature/manual/rm_cvgt_fpga_dev_board.pdf 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
0 Kudos
Altera_Forum
Honored Contributor II
1,715 Views

Thank you FvM and Anand Raj Shankar 

 

I was able to get the pin Assignment by searching a bit more on internet. 

 

As for the programming the FPGA I still have some problems, here is what I do: 

 

SW1, SW3, SW4 default configuration 

SW4: Also I tried Factory user = off 

SW5 I tried with default configuration 

SW5 I tried with MSEL1 0 and 1 

 

To activate Active Serial MSEL 0 and MSEL 1 should be 0 , 0 according to 13. Configuring Cyclone FPGAs (Cyclone Handbook Volume 1 chapter 13) 

 

 

*Quartus Prime Lite Edition Software 

Load project 

Assigments->Device->Device and Pin Options 

Configuration scheme: Active serial 1x 

Configuration device Auto 

Compile 

 

File->Converting Programming File 

Programming file type: JTAG indirect configuration file *.jic 

Configuration device: EPCQ128A/EPCS128 

Flash loader->Add device: Cyclone V / 5CGTFD9E5 

SOF Data->Add file: File.sof 

Generate 

 

*Quartus Prime Programmer Lite Edition Software 

Autodetect 5CGTFD9E5 

Select 5CGTFD9E5 click change file select file.jic 

Check Program/Configure checkbox 

Start 

 

Operation failed 

 

The error I got is  

Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.  

Error (209012): Operation failed
0 Kudos
Reply