Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Problems with ModelSIM 2020.1 Starter Edition

Gerhard56
New Contributor I
240 Views

Hi,

I finished the first version of my design and tried to simulate it. Works, but some changes requiered as usual.

Now I have to setup simulation every time from scratch. Defining the clock signal, clock periode and which signals should be in the wave panel.

As my design generate signals using a pwm, it is helpful to use the 'Analog View'. But it is boring to enter the same info over and over.

 

I searched the documentation how to save this settings, but no success. I only found something to save the results ... pretty fine but not helpful in my situation.

Please help me.

With best regards

Gerhard

0 Kudos
4 Replies
ShengN_Intel
Employee
214 Views

Hi Gerhard,

 

After making any changes to waveform like add signals, choose radix or etc in modelsim, you may save waveform format to reuse by going File -> Save Format. Will default to .do file something like …/project/simulation/modelsim/wave.do.

When you create new simulation, you can reload the waveform format by going to File -> Load -> Macro File and point to the desired .do files.

 

Best Regards

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

Gerhard56
New Contributor I
209 Views

Hi Sheng,

THAAANKS.

Worked as described.

Only one little bump in my road left. This don't restore the settings for my clock signal. I have still to right click at my clock signal and set the periode, because my periode didn't default to 100ns .. I need 83.33ns setting.

But it is much better now.

With best regards

Gerhard

ShengN_Intel
Employee
201 Views

Hi Gerhard,

 

Ya that method cannot save clock period. Sorry for confusion. For clock period you can declare it in testbench like below example:

`timescale 1ns/1ps

reg clk;

test uut(
.clk(clk));

...

initial begin

clk = 0;

forever begin 

clk = #50 ~clk;

end

end

In this example the clock period is 100ns. You can try with 83.33ns.

 

Best Regards

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

ShengN_Intel
Employee
171 Views

Hi Gerhard,


Any further update or consideration on this thread or Should I consider the case to be closed?


Best regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


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