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WMor
Beginner
761 Views

Processing Cyclone III project converted to Cyclone 10 LP gives EPCS pin configuration error.

Hello,

 

I have converted my project to Cyclone 10 LP FPGA and during processing of the project I got the following errors:

Error (12002): Port "data0_to_the_epcs_controller" does not exist in macrofunction "inst" Error (12002): Port "dclk_from_the_epcs_controller" does not exist in macrofunction "inst" Error (12002): Port "sce_from_the_epcs_controller" does not exist in macrofunction "inst" Error (12002): Port "sdo_from_the_epcs_controller" does not exist in macrofunction "inst"

I have configured the EPCS-controller pins to "use as regular I/O".

I need to write to the EPCS-eeprom after configuration because I want to remote update my system.

Can anybody help me?

 

Regards,

 

Wamor

 

 

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3 Replies
Vicky1
Employee
48 Views

Hi Wamor,

Can you please check the below solution,

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

WMor
Beginner
48 Views

Hello Vikas,

 

I am using Quartus Prime Lite Edition version 18.0.0. To generate the MegaCore I can only select Platform Designer. I have no choice to select QSys.

When I select my NIOS processor then right-click and select Open Design File then Platform Designer will be opened. After generating the processor and proces the project in Quartus I got the above mentioned errors.

Any idea what is happening? Should I rebuild my NIOS processor completely with the Platform Designer to fix the error?

 

Best regards,

 

Wamor

Vicky1
Employee
48 Views

Hi Wamor,

Actually cyclone 10 lp does not support legacy epcs/epcqx1 flash controller ip.  so use either using ASMI Parallel IP or ASMI Parallel II IP which has similar feature refer the following link,

 https://www.altera.com/en_us/pdfs/literature/ug/ug_altasmi_parallel.pdf

 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug-asmi2.pdf  

 

I tried to replicate the issue & I came across different errors but eventually I could able to do by rebuilding NIOS & ASMI Parallel IP(Instead EPCS controller).

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

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