Programming external memory via FPGA using JTAG

[Altera_Forum]

Hi, 

 I have a small serial memory device attached to a CycloneIII that I need to program during production - preferably via JTAG.  Are there tools available to pass an image file (not created in Quartus) via the JTAG interface to the FPGA?  Any hints or links to application notes would be greatly appreciated.  Ian.

[Altera_Forum]

I see basically two ways:  

- Programing the serial memory by programming logic included in your design, sending the data through any of the availiable virtual JTAG functions. I have a similar application, where the programming interface to a serial EEPROM controller is provided by a Source&Probe instance. Together with other test and debug functions, it's operated from a PC application.  - Another option, that is often used for initial programming of flash memory through JTAG capable uP, is by generic boundary scan functions, that can control any FPGA pin. All you need is the FPGAs BSDL file and an universal JTAG tool. There are some projects on the internet and commercial tools as well. The method is rather slow, cause the full scan chain has to be shifted for a single bit toggle action.

[Altera_Forum]

Hi FvM, 

 Thanks for the suggestions. Since there are only a couple of bytes to program I have included a constant that can be accessed via the memory content editor, and a source/probe to do the job.  Cheers Ian.

[Altera_Forum]

There are some open source JTAG solutions like: 

http://openwince.sourceforge.net/jtag/  Also if anyone's interested, I have a solution for using a large parallel flash device to bootload an Altera (Stratix 3) using an EPM570. This uses the (not very well documented) EPM370's ability to direct part of its JTAG chain to the user programmable part of the array.

[Altera_Forum]

We also use professional JTAG tools to do the task of programming external memories from XJTAG (and they make that process very easy), but that's $$

[Altera_Forum]

NIOS processor.

[Altera_Forum]

--- Quote Start ---  Also if anyone's interested, I have a solution for using a large parallel flash device to bootload an Altera (Stratix 3) using an EPM570. This uses the (not very well documented) EPM370's ability to direct part of its JTAG chain to the user programmable part of the array.  --- Quote End ---   In which regard is your solution different from Altera MAX II PFL design (AN386)?

[Altera_Forum]

It was based on AN386, yes, but: 

 1) Figured out how to do the rtl as verilog rather than having to use the megawizard generated function so the code can be changed to implement any flash size and/or device type required (the original was rather limited)  2) Added support for fast burst mode parallel flash to get over 50MB/sec aggregate bandwidth into the Stratix device (to meet PCI Express reset time to active requirements on a large device like an EP3SL340) during configuration  3) Figured out how to do the JTAG commands to the device in order to be able to use a faster 3rd party JTAG tool to do the initial programming.

[Altera_Forum]

Thank you for the detail information!