What is your board model/manufacturer? Unless you are forcing JTAG-based programming, aocl should try to first program the FPGA via PCI-E, and if it fails, then switch to JTAG.Also what happens if instead of programming the FPGA manually, you run your OpenCL code normally and let the FPGA be automatically reconfigured at run-time?
Hey HRZ,Using Device with name: a10gx : Arria 10 Reference Platform (acla10_ref0) Using Device from vendor: Intel(R) Corporation This is my dev kit https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html.
I get the following ouput when I compile the helloworld example and try to run the helloworld example (https://www.altera.com/support/support-resources/design-examples/design-software/opencl/hello-world....)I get this error : host: acl_pcie.cpp:71: ACL_PCIE_DEVICE* get_pcie_device(int): Assertion `0' failed. I am sure that I have connected the PCIe's well. I have installed the OpenCL image for the first time with JTAG cable. $ ./host Querying platform for info: ========================== CL_PLATFORM_NAME = Intel(R) FPGA SDK for OpenCL(TM) CL_PLATFORM_VENDOR = Intel(R) Corporation CL_PLATFORM_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 17.1.2 Querying device for info: ======================== CL_DEVICE_NAME = a10gx : Arria 10 Reference Platform (acla10_ref0) CL_DEVICE_VENDOR = Intel(R) Corporation CL_DEVICE_VENDOR_ID = 4466 CL_DEVICE_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 17.1.2 CL_DRIVER_VERSION = 17.1 CL_DEVICE_ADDRESS_BITS = 64 CL_DEVICE_AVAILABLE = true CL_DEVICE_ENDIAN_LITTLE = true CL_DEVICE_GLOBAL_MEM_CACHE_SIZE = 32768 CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE = 0 CL_DEVICE_GLOBAL_MEM_SIZE = 2147483648 CL_DEVICE_IMAGE_SUPPORT = true CL_DEVICE_LOCAL_MEM_SIZE = 16384 CL_DEVICE_MAX_CLOCK_FREQUENCY = 1000 CL_DEVICE_MAX_COMPUTE_UNITS = 1 CL_DEVICE_MAX_CONSTANT_ARGS = 8 CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE = 536870912 CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 3 CL_DEVICE_MEM_BASE_ADDR_ALIGN = 8192 CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE = 1024 CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR = 4 CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT = 2 CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0 Command queue out of order? = false Command queue profiling enabled? = true Using AOCX: hello_world.aocx Reprogramming device  with handle 1 MMD INFO : setting Cable to default value 1 MMD INFO : setting Device Index to default value 1 MMD INFO : executing "quartus_pgm -c 1 -m jtag -o "P;reprogram_temp.sof@1"" Error (213013): Programming hardware cable not detected Error (213013): Programming hardware cable not detected Error (213013): Programming hardware cable not detected mmd program_device: Board reprogram failed Kernel initialization is complete. Launching the kernel... MMD FATAL: acl_pcie.cpp:71: can't find handle -1 -- aborting host: acl_pcie.cpp:71: ACL_PCIE_DEVICE* get_pcie_device(int): Assertion `0' failed.
Hello HRZ,Yeah you were right. AOCL invokes PCIe first before JTAG. I have connected both USB and PCIe but unable to program. Should I install any kind of additional drivers to program the FPGA. I am getting the error Error (213013): Programming hardware cable not detected when I run quartus_pgm -a command. I am pretty sure the PCIe is properly connected. When I run the helloworld example I get the error MMD FATAL: acl_pcie.cpp:71: can't find handle -1 -- aborting host: acl_pcie.cpp:71: ACL_PCIE_DEVICE* get_pcie_device(int): Assertion `0' failed.
You do not need any additional drivers to program the FPGA via JTAG. However, to program it via PCI-E, you must have correctly set up your board and installed the PCI-E driver provided by the BSP and programmed your FPGA with a base OpenCL design to enable the PCI-E core on the FPGA.If your JTAG cable is connected but quartus_pgm doesn't find it, try killing "jtagd" and then running "quartus_pgm -a" as root. In my experience, it is important that after every machine reboot, quartus_pgm is first run as root or else the cable will never be detected. After that, the cable will be detected by quartus_pgm regardless of which user is invoking it. In the next step, since it seems your PCI-E core on the FPGA is broken, you probably have to reprogram the FPGA via jtag with an OpenCL design and then reboot your machine. After that, PCI-E-based programming should work.