Hello,
I am working in a Project in a Power Eletronic's laboratory and I am stucked in a part of the project. I am suposed to built a high-frequency PWM to get a high resolution in the convertion and I my only ideia does not work.
To explain what I am doing and what I am supposed to do:
I have a counter that counts the range of 0 to 4095 (12 bits) with a frequency of 100Mhz (using a PLL) utilizing the FPGA DE-0 Nano with a clock of 50MHz. Dividing the value of 100Mhz per 4095, I got a number of ~28k, but I need the value of 3 Mhz in this division, so I need to "multiply" my clock of 100 Mhz. The first action is to make the digital circuit counts in the falling edge of the clock, so I double the count of the counter. The second idea that I had it was develop lots of dephased clocks to put in paralel process, but I couldn't make a variable increment on the multiple process.
process(i_clk)
begin
if rising_edge(i_clk) then -- normal clock
acumula <= acumula +1; -- the variable that will be incremented on the two parallel process
if acumula = "111111111111" then
acumula <= (others => '0');
end if;
if acumula = "000000000111" then
else s_out_2 <= '0';
end if;
end if;
end process;
process(i_clk_defasado) -- dephased clock
begin
if rising_edge(i_clk_defasado) then
acumula <= acumula +1;
if acumula = "111111111111" then
acumula <= (others => '0');
end if;
if acumula = "000000000111" then
s_out_2 <= '1';
else s_out_2 <= '0';
end if;
end process; Help, please! :P
Sorry if I did any language mistake... I am Brazilian!
