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(QII 7.1) Don't use uppercase letters in vhdl-Generics for SOPC components

Altera_Forum
Honored Contributor II
1,723 Views

FYI. 

Background: Using QuartusII v7.1 with sopc builder. 

I used to have a problem when adding certain components to a sopc builder project. 

I had custom made components based on vhdl that had generics in the entity. When creating a component in the component editor all generics are shown as parameters in the "component wizard" tab. These parameters are editable in a dialog box when adding the component to the nios system.  

 

Adding components based on vhdl with generics to the system failed with the message: 

"An unexpected error occurred during Add Module: com.altera.utilities.altNode.AltNodeException: Premature end of file. (XML)" 

 

I filed a service request on "mySupport" @ the altera-web (https://mysupport.altera.com/). I later got the reply that the component editor has limitations in support of vhdl and verilog syntax. 

 

problem is solved by only using lower case letters in the parameter name.  

 

It works fine mixing upper and lower case in port signal names but not in generic names. 

 

I hope this info can help others to avoid the same problem.
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Altera_Forum
Honored Contributor II
1,021 Views

Thanks! That is good to know--especially since I use all caps by default. Now that I think about it, I believe I ran into this a long time ago--but never found out what the problem was.

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