Re: QSYS and double underscore in name for component make Generate HDL fail

Altera_Forum · ‎10-01-2015

Hi,

had some trouble yesterday, had an naming error in the name of an component in QSYS, it had accidental gotten the name with two underscores nios2__qsys and that breaks the HDL generate function.

Is this a bug? or is it supposed to do this?

http://www.alteraforum.com/forum/attachment.php?attachmentid=11208&stc=1

Best regards

Orjan Wean

Altera_Forum · ‎10-02-2015

Hi Orjan,

From the screenshot, seems like the HDL generation is completed successfully. Or you are referring to another screenshot?

Altera_Forum · ‎10-02-2015

Hi,

This is an screenshot from the failed generation, Done "Deca_top" with 1 module and 0 files.

I also thought it was completed successfully so took me some time to locate what was causing this.

Altera_Forum · ‎10-02-2015

It's not a documented feature (bug) - as far as I'm aware - but I have seen unwanted behaviour when renaming certain components in Qsys. Specifically, I've had issues when renaming the JTAG UART and the Nios.

Having just done a quick check: renaming the Nios component in a working system, to something with two underscores, breaks it. Renaming other components in a similar manner also breaks it.

Cheers,

Alex