Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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QSYS export a signal and use as a connection

bigcheesefuzz
Beginner
2,530 Views

Hello,

 

I'm trying to debug an FPGA / NIOS design at the moment for an intermittent bug, I'd like to bring a number of internal NIOS signals to pins on my FPGA.

 

However when I set a signal (e.g. nios2_cpu debug_reset_request) to EXPORT I then loose that signal as a connection within the qsys_system.

 

I'm looking for a way continue using a signal as a connection but also set it for Export.

 

 

 

 

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2 Replies
VVavr1
Beginner
898 Views

In the case of debug_reset_request which is Reset Output, you can solve your problem by adding Reset Bridge component to your Platform Design.

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sstrell
Honored Contributor III
898 Views

For other signals, use a pipeline bridge to connect signals internally to the system as well as be able to export them (connect them to slave side of bridge and export from the master side).

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