I'm trying to debug an FPGA / NIOS design at the moment for an intermittent bug, I'd like to bring a number of internal NIOS signals to pins on my FPGA.
However when I set a signal (e.g. nios2_cpu debug_reset_request) to EXPORT I then loose that signal as a connection within the qsys_system.
I'm looking for a way continue using a signal as a connection but also set it for Export.
For other signals, use a pipeline bridge to connect signals internally to the system as well as be able to export them (connect them to slave side of bridge and export from the master side).