Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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QSYS simulation using Avalon-MM BFM

Honored Contributor II

Hello. I'm trying to run a simulation, using a testbench, generated with QSYS: 

// qsys_mod_tb.v // Generated using ACDS version 17.0 595 `timescale 1 ps / 1 ps `define BFM qsys_mod_inst.mm_master_bfm_0 module qsys_mod_tb ( ); wire qsys_mod_inst_clk_bfm_clk_clk; // qsys_mod_inst_clk_bfm:clk -> wire qsys_mod_inst_reset_bfm_reset_reset; // qsys_mod_inst_reset_bfm:reset -> qsys_mod_inst:reset_reset_n qsys_mod qsys_mod_inst ( .clk_clk (qsys_mod_inst_clk_bfm_clk_clk), // clk.clk .reset_reset_n (qsys_mod_inst_reset_bfm_reset_reset) // reset.reset_n ); altera_avalon_clock_source# ( .CLOCK_RATE (50000000), .CLOCK_UNIT (1) ) qsys_mod_inst_clk_bfm ( .clk (qsys_mod_inst_clk_bfm_clk_clk) // clk.clk ); altera_avalon_reset_source# ( .ASSERT_HIGH_RESET (0), .INITIAL_RESET_CYCLES (50) ) qsys_mod_inst_reset_bfm ( .reset (qsys_mod_inst_reset_bfm_reset_reset), // reset.reset_n .clk (qsys_mod_inst_clk_bfm_clk_clk) // clk.clk ); // Simple check initial begin `BFM.init(); `BFM.push_command(); // <--- This line causes the error $stop(); end endmodule 

This compiles well, but elab yields the error: 

# ** Error: (vsim-8220) ./../qsys_mod_tb/simulation/qsys_mod_tb.v(37): This or another usage of 'qsys_mod_inst.mm_master_bfm_0.push_command' inconsistent with 'function' object.# Time: 0 ps Iteration: 0 Instance: /qsys_mod_tb File: ./../qsys_mod_tb/simulation/qsys_mod_tb.v 

inconsistent with 'function' object?? What? 

Moreover any call to BFM API task, except for the BFM.init, leads to the same result. 

Appreciate any help.
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Honored Contributor II

Ok, I've found that qsys generated testbench was compiled without -sv flag enabled. My solution: sel USER_DEFINED_COMPILE_OPTIONS -sv