Hi Guys,
I'm having some trouble building a system that has the ECC enabled for the on-chip memory block in QSys. I've got a HPS block running as the master h2f_axi_master on the HPS block connected to the Avalon MM Slave on the on-chip memory block.
I wish to turn on ECC on the on chip memory so that I am able to perform SDRAM scrubbing (currently I am getting the error from the Embedded Command Shell that I must activate ECC to enable SDRAM Scrubbing. Previously I've been able to SDRAM Scrub with the ECC disabled....??). Back to QSys:... I attempt to build myself the On_Chip_Memory block with ECC enabled, the AMM connection as previously described and the clock and reset as would be expected. When this is attempted the error message returned tells me I need to specify a data width of between 8 and 4096 that is a power of 2. Last I checked I'm sure 8, 16 and 32 all fulfil these requirements but I've had no joy!!!
Has anyone got any experience with this problem in this piece of IP? I can provide further information if needed!
Cheers,
Alex
