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library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mult32bit is generic ( DATA_WIDTH : integer := 32 ); port( a : in std_logic_vector(DATA_WIDTH-1 downto 0); --PARAM d : in std_logic_vector(7 downto 0); --PARAM c : out std_logic_vector((2*DATA_WIDTH)-1 downto 0) ); end mult32bit; architecture Behavioral of mult32bit is signal b : std_logic_vector(31 downto 0); signal e : std_logic_vector(23 downto 0); signal right : std_logic_vector((DATA_WIDTH)-1 downto 0); signal left : std_logic_vector((DATA_WIDTH)-1 downto 0); signal left_shifted : std_logic_vector((2*DATA_WIDTH)-1 downto 0); signal new_right : std_logic_vector((2*DATA_WIDTH)-1 downto 0); begin b <= e & d; MULTIPLIER_right:entity work.mult16bit port map( a => a(15 downto 0), b => b(15 downto 0), here is error line 42 c => right ); MULTIPLIER_left:entity work.mult16bit port map( a => a(31 downto 16), b => b(31 downto 16), c => left ); left_shifted <= left & "00000000000000000000000000000000" ; -- left_shifted <= std_logic_vector("sll"(unsigned(left), 8)); new_right <= "00000000000000000000000000000000" & right; c <= unsigned(new_right) + unsigned(left_shifted) ; end Behavioral; it is 32*32 multiplier Error: formal "b" does not exist mult32bit.vhd line 42 can anyone help me in thisLink Copied
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Where do you define e? You can't have b unless you have e defined somewhere with a value.
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This is a duplicate of this thread:
https://alteraforum.com/forum/showthread.php?t=56776 Im locking this one.
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