QUESTION on Signal Assignment of same signal and measuring times in FPGA.

Altera_Forum · ‎05-04-2018

Dear all,

can you tell me if the following is an illegal statement in VHDL 2008. I want to count up a signal read_pointer synchronously but I am not sure if the signal assignment of the same signa plus 1 will correctly synthesized:


        
address_pointer : process(CLK, RESET_H)
begin
    if (RESET_H = '0') then 
        read_pointer <= (others => '0');
        elsif (rising_edge(CLK)) then
                read_pointer <= read_pointer + '1';
        end if;
end process address_pointer;

Or do I have to make a buffering signal like this read_pointer <= read_pointer_mem + 1 and then behind the process read_pointer_mem <= read_pointer?

And I do have one further question:

What is the best way to measure a span of time in FPGA. I want to measure the span of time between two data packets. My idea was to count just the clk_cycles between the packets. Are the other ways?

Thank you.

Altera_Forum · ‎05-09-2018

Yes - use a counter to measure time, in clock cycles. That's how I would do it.

As for your code - fundamentally it's about right. What signal type are you proposing for 'read_pointer'? Depending on what that is will determine whether you need single quotes around the '1'. I'd suggest using an 'unsigned' type or an integer with a positive range. Then you wouldn't put single quotes around your + 1.

Whether you need a 'buffer' signal depends whether 'read_pointer' in a output port to your entity. You can't read output ports. So, if so, you'd need a local buffer which you'd increment and also assign to the relevant output port.

Cheers,

Alex

Altera_Forum · ‎05-09-2018

This post has no VHDL 2008 code, unless you are using numeric_std_unsigned or numeric_bit_unsigned to allow the addition of a vector and a bit/std_logic (that you are doing in the code) (but I dont think quartus supports those libraries yet).

This is really a question of logic, rather than code standard, and I think Alex has covered it.