Qaurtus automatically include files without using `include directives ?

[kikoss]

Hello

Has Quartus a have a built-in feature to automatically include files without using `include directives in our Verilog source.
Must we  explicitly specify the files to be included using  `include in the Verilog code. ? 

if a have a 3rd part IP where this is the case (they didnt used `include explicetely ) how should we expect to compile that on quartus ? (the 3rd part dont provide an altera version of the IP ) 

Thx 

Kikoss

[sstrell]

Try adding the files to the project (Project menu -> Add/Remove Files).

[ShengN_Intel]

Hi,

Other ways will be make sure the include package or file at the directory where .qpf resides. Or set the library path.

Thanks,

Regards,

Sheng

[kikoss]

Hello 

it didn't worked .. 

i want to make sure the issue is well described :

The issue is that there are some structs defined on a specific file let say fileA 

Those structs are used on project files , let say fileB 

fileA name is not included on fileB (by 3rd parts vendor IP  - asic vendor , they don't  provide quartus version)

on asic (vcs also ) flow its compiled well - by adding the location of fileA only

on quartus , it didnt compiled , so  i add the following : set_global_assignment -name SEARCH_PATH <fileA directory location >

but , quartus  get error : that the struct (defined  on fileA) is not declared 

I tried what you suggests , to copy the file on .qpf directory , but still the same error .. 

[ShengN_Intel]

Hi,

Possible to provide a minimal design for better understanding and testing?

Thanks,

Regards,

Sheng

[kikoss · Accepted solution]

@ShengN_Intel  it's a lot of work to give a minimal design based on the IP we have to compile 

However, seems we found some of the issues: 

Some issues were related to the fact that:   The `include xyz.sv is not forwarded across the hierarchy, contrary to the VCS compiler, so the solution was to add those `include and import the specific package that's defined on the `include  

Another issue was related to the timescale: we removed it from the top-level design and 

Thx for everyone about the advice