Hey Guys,I have a question concerning the Avalon Interface, especially the "fabric". Let's say I would implement all my avalon master and slave devices in VHDL on my own in, i.e. with HDL Designer. Would it be possible to import these devices in Qsys as new components and let Qsys "build" the interconnect fabric so that I don't have to implement the fabric on my own? I hope you understand my question^^ Best regards, Michl
I think you need to provide a hw.tcl file to describe your component to Qsys.See http://www.altera.com/literature/hb/qts/qsys_components.pdf (http://www.altera.com/literature/hb/qts/qsys_components.pdf)
Right, but I guess a *.tcl file is created after the whole "new component procedure" is finished successfully. Of course my component needs an avalon interface for assigning the correct signals afterwards.
If your interfaces adhere to the Avalon specifications then yes your IP should work in Qsys and the fabric will be generated automatically for you. The tools you want to take a look at is called Component Editor and it is a part of Qsys. Basically you feed it your HDL and it creates the .tcl file describing your IP so that you can choose your component just like you can choose a DMA or Nios II core from the list.