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Altera_Forum
Honored Contributor I
831 Views

compilation issues (Quartus) Please Help

Hello, 

 

I am trying to implement a mean and max module. 

 

It works on modulesim 

 

If my parameter MxN= 262144; 

 

 

--- Quote Start ---  

 

Total combinational functions 127 / 21,280 ( 1 % ) 

Dedicated logic registers 98 / 21,280 ( < 1 % ) 

Revision Name max_mean 

Top-level Entity Name max_mean 

Family Cyclone IV GX 

Total logic elements 143 / 21,280 ( 1 % ) 

Total registers 98 

Total pins 99 / 167 ( 59 % ) 

Total virtual pins 0 

Total memory bits 0 / 774,144 ( 0 % ) 

Embedded Multiplier 9-bit elements 0 / 80 ( 0 % ) 

Total GXB Receiver Channel PCS 0 / 4 ( 0 % ) 

Total GXB Receiver Channel PMA 0 / 4 ( 0 % ) 

Total GXB Transmitter Channel PCS 0 / 4 ( 0 % ) 

Total GXB Transmitter Channel PMA 0 / 4 ( 0 % ) 

Total PLLs 0 / 4 ( 0 % ) 

Device EP4CGX22CF19C6 

Timing Models Final 

--- Quote End ---  

 

 

If my parameter MxN= 362144; OR parameter MxN= 162144; 

 

 

--- Quote Start ---  

Total combinational functions 1,655 / 21,280 ( 8 % ) Flow Status Successful - Mon Sep 26 14:12:28 2011 

Dedicated logic registers 98 / 21,280 ( < 1 % ) Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition 

Revision Name max_mean 

Top-level Entity Name max_mean 

Family Cyclone IV GX 

Total logic elements 1,655 / 21,280 ( 8 % ) 

Total registers 98 

Total pins 99 / 167 ( 59 % ) 

Total virtual pins 0 

Total memory bits 0 / 774,144 ( 0 % ) 

Embedded Multiplier 9-bit elements 0 / 80 ( 0 % ) 

Total GXB Receiver Channel PCS 0 / 4 ( 0 % ) 

Total GXB Receiver Channel PMA 0 / 4 ( 0 % ) 

Total GXB Transmitter Channel PCS 0 / 4 ( 0 % ) 

Total GXB Transmitter Channel PMA 0 / 4 ( 0 % ) 

Total PLLs 0 / 4 ( 0 % ) 

Device EP4CGX22CF19C6 

Timing Models Final 

 

--- Quote End ---  

 

 

I dont know what is going on?
0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
23 Views

Neither do we, without looking at your code, but that being said: 

 

The most likely thing is your first constant is a nice power of 2 ie 262144 = 0x40000 

where as the other two value you gave are not powers of 2, so my guess is that your logic allows the synthesis tool to optimize the design to just a few gates when you have a power of 2 in your constant. 

 

Pete
Altera_Forum
Honored Contributor I
23 Views

That actually makes sense!!! 

 

But will that optimize the WHOLE module. The module performs a mean and max. 

 

here is a link to the code. I posted it in another website http://www.edaboard.com/thread225882.html#post963441
Altera_Forum
Honored Contributor I
23 Views

Also, 

 

I have state machines in my project. Is it possible to see the hardware via netlist inside the state machine on Quartus? Every 'case' is suppose to implement something.
Altera_Forum
Honored Contributor I
23 Views

The answer about the different compilation results is in this code line 

xin_mean<=xin_mean/MxN +Xin/MxN; 

It's implementing two hardware dividers respectively a simple shift operation, if MxN is a power of two. The difference also catches your eye in the Quartus hierarchy browser.
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