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Altera_Forum
Honored Contributor I
714 Views

Is Auto Gated Clock Conversion from non-pin clocks?

It's an old story. FPGA prototyping of ASIC code. Gated clocks are a big headache for timing and bigger headache to manually "fix". 

 

Auto Gated Clock Conversion would seem to be the answer but never seems to happen. 

 

After lots of searching for information and some experimentation, here is what I found: 

 

Auto Gated Clock Conversion only works if: 

 

1) The source clock is a straight line to a pin. PLL's don't work. Flops don't work ( so no clock dividing). Even lcells, instantiated global buffers and altclktrl's don't work.  

 

2) The gating is simple combinational.  

 

The second part is well known but I was really surpised about the first. What sort have designs have significant clock gating but no muxing, dividers, or PLL's? 

 

Have I missed something? Is there some way to get Gated Clock Conversion to work for an internally generated clock?
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2 Replies
Altera_Forum
Honored Contributor I
25 Views

 

--- Quote Start ---  

It's an old story. FPGA prototyping of ASIC code. Gated clocks are a big headache for timing and bigger headache to manually "fix". 

 

Auto Gated Clock Conversion would seem to be the answer but never seems to happen. 

 

After lots of searching for information and some experimentation, here is what I found: 

 

Auto Gated Clock Conversion only works if: 

 

1) The source clock is a straight line to a pin. PLL's don't work. Flops don't work ( so no clock dividing). Even lcells, instantiated global buffers and altclktrl's don't work.  

 

2) The gating is simple combinational.  

 

The second part is well known but I was really surpised about the first. What sort have designs have significant clock gating but no muxing, dividers, or PLL's? 

 

Have I missed something? Is there some way to get Gated Clock Conversion to work for an internally generated clock? 

--- Quote End ---  

 

 

Hi, 

 

I assume you missed to define the clock which is gated in the SDC-file. Have a look into the project attached. The output clock of the PLL is defined as an generated clock and the  

clock gate conversion takes place.  

 

Kind regards 

 

GPK
Altera_Forum
Honored Contributor I
25 Views

Thanks. The trick seems to be defining internally generated clock as derived from a pin clock. As least, that's how it worked in my toy design. It is going to take some work to get it into the real design. 

 

create_generated_clock -name {evil_clock} -source [get_ports {clk_in}] -master_clock {clk_in} [get_nets {clk_divider:cdiv|clkOut}]
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