Quartus II Web Edition 10.0 SP1 : EDA Gatele level simulation

[Altera_Forum]

Hello, 

 I'm new with the ModelSim-Altera (i' known well Max+Plus II and the embedded version of simulation in the previous version of Quartus).     I have readed Quartus Handbook and Help, lot of threads in the Forum but I did’nt found the answer. So I post this one.    I’ve reduced my problem to the smallest ones to simulate one selector (selector.vhd). After the proposed modification in the Assignments Settings menu (Format for output netlist è vhdl, Map illegal HDL character è on, Compile test bench è T1 for the use of the benches file : “selector_test.vhd”. The EDA Tool settings for simulation are turned on ModelSim-Altera, with VHDL format.    I’ve no problem with the RTL simulation, but some ones with the gate level ones.Modelsim (ModelSim Altera starter edition 6.5e) write in the transcript aera :  # Loading instances from selector_vhd.sdo# ** Error: (vsim-SDF-3250) selector_vhd.sdo(0): Failed to find INSTANCE '/selector'.# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s).# ** Error: (vsim-SDF-3250) selector_vhd.sdo(0): Failed to find INSTANCE '/selector'.# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./selector_run_msim_gate_vhdl.do PAUSED at line 12   What i forgot in the settings of Quartus II to use this new EDA-Tools (for me !)   Thanks and best regards EON

[Altera_Forum]

--- Quote Start ---  Hello,  I'm new with the ModelSim-Altera (i' known well Max+Plus II and the embedded version of simulation in the previous version of Quartus).     I have readed Quartus Handbook and Help, lot of threads in the Forum but I did’nt found the answer. So I post this one.    I’ve reduced my problem to the smallest ones to simulate one selector (selector.vhd). After the proposed modification in the Assignments Settings menu (Format for output netlist è vhdl, Map illegal HDL character è on, Compile test bench è T1 for the use of the benches file : “selector_test.vhd”. The EDA Tool settings for simulation are turned on ModelSim-Altera, with VHDL format.    I’ve no problem with the RTL simulation, but some ones with the gate level ones.Modelsim (ModelSim Altera starter edition 6.5e) write in the transcript aera :   # Loading instances from selector_vhd.sdo # ** Error: (vsim-SDF-3250) selector_vhd.sdo(0): Failed to find INSTANCE '/selector'. # ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving instances from compiled SDF file(s). # ** Error: (vsim-SDF-3250) selector_vhd.sdo(0): Failed to find INSTANCE '/selector'. # Error loading design # Error: Error loading design  # Pausing macro execution  # MACRO ./selector_run_msim_gate_vhdl.do PAUSED at line 12   What i forgot in the settings of Quartus II to use this new EDA-Tools (for me !)   Thanks and best regards EON  --- Quote End ---    Hi,  Quartus generates two files for the modelsim simulation.  1. <toplevel_name>_vhd.sdo ( this file contains the timing information) 2. <toplevel_name>.vho ( this file contains your design gatelevel)  You need both file files for the simulation. I assume you forgot to include the <toplevel_name>.vho file.   Kind regards  GPK

[Altera_Forum]

Hi, 

I had read such informations in the forum and Altera's documentation, but this files have been created by the EDA Tools (or the simulator, i don't know) in the sub-repertory simulation/modelsim.  I put in attach file a zip, with the selector project, selector vhdl file and selector_test vhdl file. I had the sub-repertory simulation/modelsim.   The main strange thing is that the RTL simulation (trough the menu tools/run simulation eda tool/ eda rtl simulation ) is functional without warning.  The Settings/EDA Tool Settings for simulation are :  

• Tool Name : ModelSim-Altera 
• Format for output netlist : VHDL 
• output directory : simulation/modelsim 
• Map illegal HDL characters: on 
• Compile test bench : T1 ==> 
• top level module in test bench : selector_test 
• Use test bench to perform VHDL timing simulation : on 
• Design instance name in test bench : selector 
• Run simulation until all vector stimuli are used : on 
• test bench files : selector_test.vhd 

 I found an example for simulation with native-link and ModelSim-Altera in Verilog (Native_Modelsim_restored : multiplier project) and tried it with no problem for RTL and gate level simulation, so it seem's that it is not a problem with my version of Quartus.  So, i begin to have no more ideas. thanks for your time,   EON

[Altera_Forum]

Hi EON 

I ran into the same problem today. Turned out I had to set the Test Bench settings right. In  

• Use test bench to perform VHDL timing simulation : on 
• Design instance name in test bench : selector 

 Change your Design instance name to inst_selector. This worked for me, hope it'll work for you. Patrice

[Altera_Forum]

Hy Fabrice, 

 I tried your solution and i obtain the gate level simulation, so thank's. It was difficult to find such informations, i did not read anything on this constraint on the instance name.  So i continue my exploration of this new version of Quartus.  Best regards,  EON.

[Altera_Forum]

Finally, the Design instance name ('inst_selector' for example) to use in the edit test bench settings, is the name given for the instance of the component in the test bench files : 

 inst_selector : selector PORT MAP (A, B, Sel, S);  If this name of instance change, the name in the settings muts change and could be not linked to the filename.  EON

[Altera_Forum]

Hi Guys, 

I am having the exact same problem however all my entity naming conventions match. I am having a little trouble finding where I can change the afford mentioned Test bench setting    --- Quote Start ---  Use test bench to perform VHDL timing simulation : on  --- Quote End ---   Were can I find this in model sim? or do i have to apply these setting in Quartus?

[Altera_Forum]

Hi,  

Please take this with a grain of salt. I use NativeLink sparsely and I don't have the tools at hand to confirm.  In ModelSim the /x/ will be top level entity *of the simulation*, which should be your test bench.  So, when modelsim complains about /selector/ which is your module's name, it suggests you've mixed up your module's name, the instance name and your testbench's name.  So, let's assume your test bench look something like this: entity selector_tb is end entity;  architecture behavioral of selector_tb is  begin ... uut : selector port map ( blablabla); ... end behavioral;  Your testbench's entity name is "selector_tb". The module's entity name is "selector" but it's instance name within you testbench is "uut", "uut" stands for unit under test, in case you wonder.  IIRC, when setting up native link, you need to tell it both the testbench's entity name (selector_tb) and the instance name in your testbench (uut).  So, in ModelSim you'll have an hierachy like selector_tb/ +- dut/  +- selector's contents +- other stuff in your test bench

[Altera_Forum]

Great explanation, 

It worked  Thank you so much