Qsys-DDR2_SDRAM Configuration

[Altera_Forum]

Hi, 

 I´m new in the IP Core design. I`m using a Cyclone III 3C120 Development Board and now I want to design an IP Core with the following parts: clock source, Nios II Processor, Character LCD, PIO, On-Chip-Memory, DDR2 SDRAM Controller with ALTEMEMPHY. My problem now is: If I choose the DDR2 SDRAM a Warning appear.  Warning: System.altmemddr_0: Cyclone III speed grade 7 does not support DDR2 SDRAM operation above 167.0MHz.  In my understanding I just say, that I can´t drive this SDRAM over a frequency of 167MHz.   So my question is:  Should I change the configuration of the memory? And if I need to do this, how can I do it? And which things do I need to change and where I can find them?  Thanks for your reply!

[Altera_Forum]

Lower the frequency of memory controller in DDR2 component settings. I've tested the same board with 125MHz and it worked fine.

[Altera_Forum]

Thanks, I tried it and it works.  

But I need to fit also the "Read to Precharge time(tRTP)" from 7.5ns to 8.8 ns.

[Altera_Forum]

It's also changable in the core parameters.