Qsys and basic signals

[Altera_Forum]

Hello All. 

  Have problem with simple project with qsys. I am use onchip ram, and want write to address 0x000_000 2 bytes. I am add in qsys altera master template, all connect and 0 errors, next step generate hdl and add to empty project. add hardware clock with same name in generate hdl and no question - i am try to many iterations for work with signals - and not understand WHAT signal need use for work. Read all manuals for avalon mm, handbook and look video tutorials and etc. May be you have time help understand me job this process ?  Me need only understand what signal from generate hdl file use need for write to on chip memory. top level design and screen qsys i am add.  Thank you for help.

[Altera_Forum]

What do you want to write to your on-chip RAM with? One option is to use a Jtag->Avalon Master Bridge and then use something like System Console to write to the onchip RAM. 

 If you want to do it in VHDL, then you can double-click the Slave port on the RAM and export the signals. Then your top level file will include the Qsys component (see Generate->Show Instantiation Template...) for the component signals. This should show you your clock and reset signals, and the avalon_mm addr, data, be, read, write, and q signals.

[Altera_Forum]

simonkbrown 

 Hello, Thank you for answer. Exactly yes - i am want write few bytes to on chip memory via VHDL and avalon mm bus. Now i am remove master template, export slave and have in entity next:  Use this for write or read - this input pins i am dont understand what. Sorry , i am really want understand avalon bus working logic. Thank you for answer.  entity hd_mem is  port (  clk_clk : in std_logic := '0'; -- clk.clk  onchip_mem_s1_address : in std_logic_vector(10 downto 0) := (others => '0'); -- onchip_mem_s1.address  onchip_mem_s1_clken : in std_logic := '0'; -- .clken  onchip_mem_s1_chipselect : in std_logic := '0'; -- .chipselect  onchip_mem_s1_write : in std_logic := '0'; -- .write  onchip_mem_s1_readdata : out std_logic_vector(15 downto 0); -- .readdata  onchip_mem_s1_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata  onchip_mem_s1_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable  reset_reset_n : in std_logic := '0' -- reset.reset_n  ); end entity hd_mem;

[Altera_Forum]

Ok, so you now have the address, clken, signals etc. To write a word to the memory you need something along the lines of: 

 process(clk) if (rising_edge(clk)) then  addr <= addr + 1;  clken <= '1';  chipselect <= '1';  write <= '1';  writedata <= X"1234";  byteenable <= "1111"; end if; end process;  This will (assuming addr is initialised on a reset signal or similar) fill your memory with 0x1234 and increment the address every clock cycle. Obviously you can change the write data each clock cycle, or you can pause the write with setting "write <= '0'" when not ready.  Basically to write a word, setup the address, chipselect, clken, write, byteenable and writedata signals, and keep them there for a clock cycle (the same clock that you clock the memory with). To read a word you need address, chipselect, and clken and the data will appear on the following clock cycle on the readdata bus.

[Altera_Forum]

2 simonkbrown 

 Hello. Thank you for you are answer. So i am try all my ideas write to on-chip memory with use qsys.  My last step - i am remove all, add only onchip memory, all exports and try this - result every time same - signals from qsys not drived. May be you have little time for understand this process ? I am think for to many guys its be good help. In attach - sreen from qsys, top level and signaltap screen.  Thank you for understand.

[Altera_Forum]

But you need to attach the signals from your process to the signals from the onchip ram - so: 

 onchip_mem : hd_mem_onchip_mem port map ( clk => clk, address => address, clken => clken, etc.  In your internal scope you are watching the onchip_mem signals, but nothing is driving them - hence they default to 1.   The onchip_mem signals you've got on your entity hd_mem, so they are coming in from outside the chip at the moment - do you have anything driving these?  You say in your original post that you want to write 2 bytes - where is the data you want to write coming from? This ultimately needs to connect to the writedata bus to your onchip memory.

[Altera_Forum]

Hello. 

 So, i am change in top level:  -- onchip_mem : component hd_mem_onchip_mem -- port map ( -- clk => onchip_mem_clk1_clk, -- clk1.clk -- address => onchip_mem_s1_address, -- s1.address -- clken => onchip_mem_s1_clken, -- .clken -- chipselect => onchip_mem_s1_chipselect, -- .chipselect -- write => onchip_mem_s1_write, -- .write -- readdata => onchip_mem_s1_readdata, -- .readdata -- writedata => onchip_mem_s1_writedata, -- .writedata -- byteenable => onchip_mem_s1_byteenable, -- .byteenable -- reset => onchip_mem_reset1_reset, -- reset1.reset -- reset_req => '1' -- (terminated) -- );     onchip_mem : hd_mem_onchip_mem   port map ( clk => clk, address => address, clken => clken, chipselect =>chipselect, write => write, writedata => writedata, byteenable => byteenable, reset => reset, reset_req => reset_req );  And result similar, bus not driving. From outside - i am not driving this signal and me very intresting what need add this is signal to top-level. And about write data - yes i am have array from very slow process, now i am simply write data to register and now for expirience want accum. data to internal ram.  If posiible from you are side help - its be nice.  In all cases now - this simple project dont write any to on-chip. Me need only one time understand this process.   Thank you for understand.