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Altera_Forum
Honored Contributor I
3,513 Views

Qsys component editor: No modules found when analyzing null

Hello, I am facing a strange Qsys problem when trying to add new components. After I added the synthesis files, I click on "Analyze Synthesis Files" and the appearing dialog says me, that there are no modules. 

I have checked that the files are available and accessable. I also uninstalled and reinstalled Quartus and switch to verison 16.1. But the problem stayed, also when I give Quartus admin rights (not sure if this affects Qsys anyway). 

Has somebody faced such a problem previoulsy or has any idea how to solve this? (I have seen the note in Altera Wiki on SystemVerilog, but I only use VHDL). Thank you! 

http://www.alteraforum.com/forum/attachment.php?attachmentid=13149&stc=1
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10 Replies
Altera_Forum
Honored Contributor I
409 Views

I have the exact same problem. 

I'm using Quartus 14.1 trying to create QSYS components from VHDL files. 

Analyze Synthesis Files gives the error message "No modules found when analyzing null." 

Haven't found any solutions yet. I'll get back here if I find something.
Altera_Forum
Honored Contributor I
409 Views

This is a known problem for some years now. If the file has an synthesis error, no matter how minor, you will likely get this message. It is supposed to tell you the error in some meaningful way, but this is usually what you get. The only workaround I've found for this is to create a dummy project just for the component and try to synthesize it, find and fix your errors, then go back to your real project and build the component as before.

Altera_Forum
Honored Contributor I
409 Views

Well, when I load the file in Quartus I can synthesize it and in ModelSim I did not find any error, simulations ran as expected. But I will try to use the component Editor with a file which only routes the clock signal through, maybe this works. I will come back when I have tested it.

Altera_Forum
Honored Contributor I
409 Views

Problem solved for me. I had a typo in the vhdl source file. 

I suspect that it can also be affected by what language version of VHDL you are using. (-87, -93, -2002 or -2008) 

Found this: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05312011_49.html
Altera_Forum
Honored Contributor I
409 Views

I have had the same problem in QSYS, it is very irritating. I have been working around it by doing the HDL analysis at the command line. This allows you to check a single file at a time but at least gives some decent output that helps find the syntax errors. 

 

quartus_map <project_name> --analyze_file=<filename and path> 

 

This will find syntax errors. 

Note that you don't actually need an active project to run this command. You can just fill project name with any text, it just needs something, it will create a base project for you. 

 

Once you have a base project you can re-run the command without the --analyze_file hook to do basic synthesis analysis.
Altera_Forum
Honored Contributor I
409 Views

In previous versions of Quartus, there was an option to have the tool analyze the current design file. That way, you would have the same analysis performed as what is happening in Component Editor and get actually useful info on how to fix errors. But that was removed at some point for some reason. This is a known bug in Component Editor. I actually just filed it as a bug recently and hopefully it will get fixed this year. 

 

Ahh just noticed ArcticRain above has a workaround I didn't know about using the command line!
Altera_Forum
Honored Contributor I
409 Views

What if the error (in qsys) still appears and even the command line doesn't spot the error(in the code)? :) 

 

 

apparantly Quartus prime doesn't care about 100% correct indentation, Qsys does. 

fixing indentation solved my issue.. 

 

update: After spending some more time on this: There seems to be some randomness with this error. An "wrong" line of code would trigger the error, after retyping exactly the same line, the error would de gone. it's a weird bug? :confused:
Altera_Forum
Honored Contributor I
409 Views

This helped me a lot, thank you!  

I had one more step to get it to stop with the "null" thing even after fixing the syntax errors: My source file has some System Verilog in it, so I renamed it from myfile.v to myfile.sv and then it finally accepted it.  

BitBuster's comment above on VHDL version twigged this idea for me.  

(I'm using Quartus 14.1 for the record).
Altera_Forum
Honored Contributor I
409 Views

Just following on to this post. My initial command line command only provides a basic syntax check. To get a full aelaboration from the command line use the following: 

quartus_map <project_name> --analysis_and_elaboration --source <filename and path>
DGant
Beginner
409 Views

As one of the earlier comments mentioned, adding -- altera vhdl_input_version vhdl_2008 at the top of the file solved the error. Qsys was able to analyze the file.

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