While it is not officially supported (I cant find it in any coding guidelines) it has been supported by many tools for many years.
In VHDL, one liners like this actually infer a process sensitive to all signals on the RHS. So
q <= d when rising_edge(clk);
is functionally identical to
process(clk, d) -- D not needed, but it is needed for full equivolence to one liner. begin if rising_edge(clk) then q <= d; end if; end process;
Thanks for the answer.
It may not be supported coding style for inference of flip-flops, and it is used very little, if at all in practice, so may be OK not to support in Intel coding guidelines.
However, the coding style makes Quartus 18.1 break with internal error, which indicates a bug in the tool.
? Any suggestion for how I can report this bug ?
This code line is standard synthesizable code.
It was specified in IEEE Std. 1076.6-2004 Clause 184.108.40.206
220.127.116.11 Edge-sensitive storage using concurrent signal assignment statements
A concurrent conditional signal assignment statement may be used to model an edge-sensitive storage element
provided that the assignment can be mapped to a process that adheres to the rules in 18.104.22.168.
COND_SIG_ASSGN: Q <= '0' when RESET = '1' else '1' when SET = '1' else A when ASYNC_LOAD = '1' else D when CLOCK'EVENT and CLOCK = '1';
More over it was supported by previous Quartus versions as this tool was called "Altera Quartus II".
Even if it's an unsupported syntax, a tool should never crash.
In addition, this syntax is supported by all competitors (I'm listing only synthesizer tools):
- Xilinx ISE
- Xilinx Vivado
- Lattice LSE
- Synopsys Simplify PRO
Vice-Chair of the IEEE P1076 Working Group
I tried to recreate the problem, in order to do a bug report in this issue:
However, I was unable to recreate the problem again, so for now I cant look further into this with respect to the Quartus error.