Qsys custom component and .qip file paths with subfolders

[Altera_Forum]

Hi all, 

 I'm having some issue with Qsys generating a hierarchical system, made of a main_system.qsys system and an adc_subsystem.qsys (plus other subsystems) and in the adc_subsystem I use a custom Qsys component, adc_controller, that instantiates a PLL (created with the ALTPLL from the IP Catalog, not from Qsys).  This is my how my project folder looks like:  ..\<main folder> - with .qpf, .qsf , top level HDL files and custom build scripts ..\<main folder>\qsys - with all the .qsys files for systems and subsystems ..\<main folder>\qsys\ip\adc_controller\ - juts the <component name> _hw.tcl file ..\<main folder>\qsys\ip\adc_controller\rtl - component HDL files ..\<main folder>\qsys\ip\adc_controller\sim - simulation stuff (testbenches and ModelSim files)  I generate the PLL IP variation file, adc_clk_rx_pll.v in the ..\adc_receiver\rtl\ and this is what the content looks like after Quartus generates the IP:   ..\<main folder>\qsys\ip\adc_controller\rtl\adc_clk_rx_pll.v ..\<main folder>\qsys\ip\adc_controller\rtl\adc_clk_rx_pll.qip ..\<main folder>\qsys\ip\adc_controller\rtl\adc_clk_rx_pll\adc_clk_rx_pll_0002.v ..\<main folder>\qsys\ip\adc_controller\rtl\adc_clk_rx_pll\adc_clk_rx_pll_0002.qip  The relative new subfolder seems to create a problem because I added all the files (including the ones in the ..\adc_clk_rx_pll subfolder) in the ..\rtl folder and this is what the _hw.tcl section looks like:  add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL adc_controller set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS true set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false add_fileset_file adc_clk_rx_pll.v VERILOG PATH rtl/adc_clk_rx_pll.v add_fileset_file adc_ddr_rx.v VERILOG PATH rtl/adc_ddr_rx.v add_fileset_file ads5474_avmm_registers.v VERILOG PATH rtl/ads5474_avmm_registers.v add_fileset_file ads5474_multisample_output_interface.v VERILOG PATH rtl/ads5474_multisample_output_interface.v add_fileset_file ads5474_receiver.v VERILOG PATH rtl/ads5474_receiver.v add_fileset_file ads5474_sample_fifo8x14.v VERILOG PATH rtl/ads5474_sample_fifo8x14.v add_fileset_file ads5474_sample_fifo8x32.v VERILOG PATH rtl/ads5474_sample_fifo8x32.v add_fileset_file ads5474_singlesample_output_interface.v VERILOG PATH rtl/ads5474_singlesample_output_interface.v add_fileset_file adc_controller.v VERILOG PATH rtl/adc_controller.v TOP_LEVEL_FILE add_fileset_file adc_clk_rx_pll.qip OTHER PATH rtl/adc_clk_rx_pll.qip add_fileset_file adc_ddr_rx.qip OTHER PATH rtl/adc_ddr_rx.qip add_fileset_file ads5474_sample_fifo8x14.qip OTHER PATH rtl/ads5474_sample_fifo8x14.qip add_fileset_file ads5474_sample_fifo8x32.qip OTHER PATH rtl/ads5474_sample_fifo8x32.qip add_fileset_file adc_clk_rx_pll_0002.qip OTHER PATH rtl/adc_clk_rx_pll/adc_clk_rx_pll_0002.qip add_fileset_file adc_clk_rx_pll_0002.v VERILOG PATH rtl/adc_clk_rx_pll/adc_clk_rx_pll_0002.v   But when I generate the HDL from Qsys the \adc_clk_rx_pll gets flattened out and now the files cannot be found anymore and hierarchy elaboration fails:  Warning (125092): Tcl Script File qsys/main_system/synthesis/submodules/adc_clk_rx_pll/adc_clk_rx_pll_0002.qip not found  Info (125063): set_global_assignment -name QIP_FILE qsys/main_system/synthesis/submodules/adc_clk_rx_pll/adc_clk_rx_pll_0002.qip -qip qsys/peanuts_main_system/synthesis/submodules/adc_clk_rx_pll.qip -library adc_clk_rx_pll   but this is the content of my main_system.qip file  I tried to generate juts the subsystem in which the adc_controller component is instantiated but same problem: the relative subfolder path is not kept. Everything is flattened out in a single output folder. How can I solve this problem? I tried to tweak the set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS , setting it to true but it doesn't seem to help.  I could manually tweak the PLL .qip files to remove the relative path but that will create issues if I have to regenerate the PLL IP. Am I playing a dangerous game because of the way I organized my project file structure? Of course adding the .qip directly to the files list in Quartus fixes the issue but a nice thing about the component definition in Qsys is that is supposed to keep everything defined in the _hw.tcl file.  Help..... please...

[Altera_Forum]

I tried a couple of simple hierarchical systems with QSYS before giving up and concluding that it just doesn't work yet. Perhaps it will be fully implemented in a future tools version. I'd advise not wasting further time with it until then.

[Altera_Forum]

My experience so far is actually quite positive with hierarchical systems and all my project is hierarchical at this point. Working with Quartus 14.1.1. 

This is the first hiccup I have.  Altera folks, would you please chime in?

[Altera_Forum]

I would like to understand this too. I think my problem is a little simpler, but shows similar quirky behavior of the tools when it comes to custom IP blocks. 

 In my project root directory I put my custom qsys IP in an "ip" directory. When I bring those components in, the _hw.tcl and verilog code exist within that directory.  When I generate the Qsys system, sometimes my verilog code file is copied into the qsys_system_name/synthesis/submodules directory as it was when it was generated. Thus, when I edit the code in my ip directory, the changes do not get compiled when I build in quartus (it gets update if I regenerate).  If I update the IP block in my ip directory, update the IP block to the new version in Qsys and generate, it creates a zero-size file of the same name in the synthesis/submodules directory -- but in this case if I rebuild the system with quartus, it will use the original source file for the compile.   I briefly tried to force the paths based on some advice given by others but ultimately failed to get it to work -- maybe an answer to your questions will shed some light on the ones that I have seen.  Lance

[Altera_Forum]

I got the zero-size file problem too sometimes, but I haven't unraveled yet the sequence of operations that cause it.  

However I got rid of it mostly by carefully refreshing (F5) the system after each IP version bump.

[Altera_Forum]

Dear all, 

 Please have a look at this : http://www.alteraforum.com/forum/showthread.php?t=49013.  It contains some useful information.  Cheers, Bhaumik

[Jodok]

Hi, I am encountering the exact same problem. I also have a pll that I have included in a subsystem with hirarchy.

Have you found any solution yet?