Hi all,
I'm having a Qsys issue and was wondering if anyone has experienced this. I'm using Quartus 15.0 and 15.1 (tested on both), and Statix V.
There is an QDR-II memory interface using UniPHY that works correctly on my board. This interface features a separate Avalon MM read port and Avalon MM write port, called avl_w and avl_r. Using these interfaces everything works great. Each Avalon interface presents a 72-bit data interface with 9-bit symbols. This is interfaced to my logic.
It is needed to have two masters that can both use this QDR interface, which would require some arbitration logic, which is just fine. To my knowledge, the arbitrator is auto-inferred when two Avalon masters are connected to the one slave. I brought in 2 Avalon MM pipeline bridges and connected their master side to the same avl_r. Got an error - "Data width must be a power of two and between 8 and 4096". It's having a problem with the fact that my data size is 72 and each symbol is 9 bits. But that's the point of having symbols, for irregular sizes!
Is there a way to bring in an explicit arbiter into the system? Is there some other way of handling this or do I have to write my own arbiter?
Thanks!
