Hi,
In my design I have a number of Altera IPs such as a DDR3 memory controller, and I have a couple of VHDL modules that are written in-house.
When I try to generate a testbench, i.e. "Create simulation model: Verilog", Qsys tells me that it cannot generate simulation models for my VHDL modules, and aborts.
In Altera Knowledge Base solution rd11152011_763 I found that I could set set_module_property "simulationModelInVerilog" "true" in the _hw.tcl file for my VHDL modules.
This seemed to solve my problem, since Qsys now generated the simulation model without complaints.
But here's the problem: When Qsys generates the simulation model it replaces my VHDL modules with dummy Verilog modules.
I call these modules "dummy", since all they do is to assign outputs to constants!
So, does anyone have a solution for this problem? Or any suggestions for a way forward?
