Qsys project re-generate issue(PCIe in Qsys for StratixIVGX)

[Altera_Forum]

Hi guys, 

 I just download the example project(PCIe in Qsys for StratixIVGX) from wiki, and open Qsys to generate it again, I didn't change anything. However, i got this errors http://www.alteraforum.com/forum/attachment.php?attachmentid=9824&stc=1  It seems powerdown signal in primary project is float, these error tell me to export this signal outside Qsys and connect to somewhere. My QII version is 12.1+sp1. My question is why this happens when i re-generate?

[Altera_Forum]

This is simple: 

As the error already says: Export them! To put it quick: if you do not use a port in QSYS, export it to the "Outside". There you can connect it to Ground, Vcc or other logic.  For the powerdown-ports especially you can invert the PCIe_reset_n and use it as Input to powerdown. As I know this is also the way it's done in the Altera design example.  PS: for good digital design: EVERY input has to be connected to something. For example if you don't use some Inputs of an OR-Gate, wire them to ground. If you don't use some Inputs of an AND-Gate, wire them to Vcc. Inputs which are "dangling in the Air" produces unexpected behaviour.

[Altera_Forum]

--- Quote Start ---  This is simple: As the error already says: Export them! To put it quick: if you do not use a port in QSYS, export it to the "Outside". There you can connect it to Ground, Vcc or other logic.  For the powerdown-ports especially you can invert the PCIe_reset_n and use it as Input to powerdown. As I know this is also the way it's done in the Altera design example.  PS: for good digital design: EVERY input has to be connected to something. For example if you don't use some Inputs of an OR-Gate, wire them to ground. If you don't use some Inputs of an AND-Gate, wire them to Vcc. Inputs which are "dangling in the Air" produces unexpected behaviour.  --- Quote End ---    Hi Steffen,   Thanks for you reply, it's OK now! The next step is to add my own fifo inside Qsys.

[Altera_Forum]

I've made a screenshot of my exported ports of PCIe outside of QSYS.

[Altera_Forum]

--- Quote Start ---  I've made a screenshot of my exported ports of PCIe outside of QSYS.  --- Quote End ---    I got it, thank you very much.