Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus 11.1 incorrectly compiles the design

Altera_Forum
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Has any one else seen this? 

Q 11.1 incorrectly compiles the design. When trying the same code, qsf, sdc and rest of the project with Q 11.0 sp1, the design is compiled correctly. I do not see any timing errors in Q 11.1 compile. 

 

At present, the only way I can tell that the design doesn't function is by seeing ip hdr chksum errors on the network sniffer.  

 

Any pointers, suggestions while I continue to debug this?  

 

Thanks. 

Sanjay
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Altera_Forum
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I suggest you try to build in a signal tap to examine and try to isolate what's failing. 

 

So far I haven't had any issues with 11.1 but it may be very specific issue with the code you are compiling. 

 

If you can isolate it down to a single section of code, that's in error, you can open a service request to see if you can get a hotfix for it. 

 

I would also double check any false path statements. It may be that the timing across a "false Path" is really critical, and the to routers just placed the logic differently, causing it to run or fail. 

 

Pete
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Altera_Forum
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Everyone using 11.1 should add the following patch: 

 

http://www.altera.com/support/kdb/solutions/rd11182011_10.html
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Altera_Forum
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Rysc, 

 

This did the trick. 

 

Thank you.
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