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[Quartus 17.0] Internal Error: Sub-system: CCLK, File: /quartus/periph/cclk/cclk_gen5_base.cpp, Line

Hello there,

I'm trying to add a second external clock source to a design implemented on a DE10-Standard Kit. I'd like to use the J14/HSMC_CLKIN0 pin as single-ended clock source actually, then use it as a PLL reference clock. It is the only PLL in the design I need to generate several frequencies (consuming a integer and a fractional PLL resource on the FPGA for the implementation).

If I add a pin to my BDF file the fitter crashes with this error:

Problem Details
Internal Error: Sub-system: CCLK, File: /quartus/periph/cclk/cclk_gen5_base.cpp, Line: 4101
Stack Trace:
    0xaa963: CCLK_GEN5_MODULE::create_pll_counter_cascading_routing_restrictions + 0x6a0b7 (periph_cclk)
    0x40b0a: CCLK_GEN5_MODULE::alter_design + 0xbe (periph_cclk)
     0xfa67: PCC_ENV_IMPL::perform_op + 0x28b (periph_pcc)
     0xf75b: PCC_ENV_IMPL::create_design + 0xef (periph_pcc)
   0x11179d: FITCC_PERIPHERY_FLOW::placer_setup + 0x10d (FITTER_FITCC)
   0x10ed54: FITCC_PERIPHERY_FLOW::do_placement + 0xa4 (FITTER_FITCC)
   0x111642: FITCC_PERIPHERY_FLOW::placer_finish + 0x242 (FITTER_FITCC)
   0x10ed74: FITCC_PERIPHERY_FLOW::do_placement + 0xc4 (FITTER_FITCC)
    0x25ac1: FSV_EXPERT::fitter_preparation_run_fpp + 0x81 (fitter_fsv)
    0x238f1: FSV_EXPERT::fitter_preparation + 0x31 (fitter_fsv)
    0x1dfff: FSV_EXPERT_BASE::fitter_preparation_run_family_fitter_preparation + 0x4f (fitter_fsv)
    0x1daf8: FSV_EXPERT_BASE::fitter_preparation + 0x68 (fitter_fsv)
    0x1e750: FSV_EXPERT_BASE::invoke_fitter + 0x3b0 (fitter_fsv)
    0x1c872: fsv_execute + 0x22 (fitter_fsv)
     0xe900: fmain_start + 0x900 (FITTER_FMAIN)
     0x41b1: qfit_execute_fit + 0x1bd (comp_qfit_legacy_flow)
     0x5384: QFIT_FRAMEWORK::execute + 0x2a0 (comp_qfit_legacy_flow)
     0x267f: qfit_legacy_flow_run_legacy_fitter_flow + 0x1c7 (comp_qfit_legacy_flow)
    0x14410: TclInvokeStringCommand + 0xf0 (tcl86)
    0x161e2: TclNRRunCallbacks + 0x62 (tcl86)
    0x17a65: TclEvalEx + 0xa65 (tcl86)
    0xa6f8b: Tcl_FSEvalFileEx + 0x22b (tcl86)
    0xa5646: Tcl_EvalFile + 0x36 (tcl86)
    0x12606: qexe_evaluate_tcl_script + 0x376 (comp_qexe)
    0x11864: qexe_do_tcl + 0x334 (comp_qexe)
    0x16755: qexe_run_tcl_option + 0x585 (comp_qexe)
    0x380c3: qcu_run_tcl_option + 0x1003 (comp_qcu)
    0x160aa: qexe_run + 0x39a (comp_qexe)
    0x16e51: qexe_standard_main + 0xc1 (comp_qexe)
     0x2233: qfit2_main + 0x73 (quartus_fit)
    0x12d68: msg_main_thread + 0x18 (CCL_MSG)
    0x1454e: msg_thread_wrapper + 0x6e (CCL_MSG)
    0x15b00: mem_thread_wrapper + 0x70 (ccl_mem)
    0x12631: msg_exe_main + 0xa1 (CCL_MSG)
     0x287e: __tmainCRTStartup + 0x10e (quartus_fit)
    0x12773: BaseThreadInitThunk + 0x13 (KERNEL32)
    0x70d50: RtlUserThreadStart + 0x20 (ntdll)


Executable: quartus_fit

System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0

Quartus Prime Information
Address bits: 64
Version: 17.0.0
Build: 595
Edition: Standard Edition


I'm getting this annoying error regardless:

  • the actual pin I assign to the input clock source (tried some GPIO as well already...)
  • removing the PLL and using the pin to drive a simple test counter entity...
  • using a ALTCLKCTRL block (on auto)

No reference around. Hope you can help me sort it out...

0 Kudos
1 Reply

Hi Luca,

Could you provide the design file for me to replicate the issue? You can attach it via private message/email feature there. Let me see it first, if it a bug from Quartus I can file a report for this.