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Honored Contributor I
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Quartus 2 7.0 download

Where can i download the free version of quartus 2 7.0, its the version my uni uses and i want to do the work on matching versions, also i tried doing the same file in 7.2 and it gave an error, i made the exact same file, in the morning and it was fine in the lab, i changed the way the pins were named from A[3..0] to A3,A2,A1,A0 and it worked, so i want quartus 2 7.0 because it seems to be better than 7.2, can someone point me to where i can download it, 

 

Thanks // Ace 

 

Edit: i'm using Q2 7.2 build 151, have i downloaded beta software by accident or something? 

 

Edit: I found the 7.0 30 day trial version, but not the free version, no longer available for download? 

 

Edit: You know the free web edition of 7.2, should i be able to compile stuff in it? it said something like specified license does not contain information required to run quartus 2 software or did i install the license wrong? btw i got this error when i went with the 30 day trial option on the license options dialogue box which pops up on each startup
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Honored Contributor I
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ftp://ftp.altera.com/outgoing/release/70_quartus_free.exe 

 

Is the site to for the free version of 70. It sounds like your real problem is a licensing issue. 

 

For the 30 day eval licenses, you have to request that license from Altera. Quartus has a request option. 

 

I'm currently running a build right now, so I can't tell you where it's located exactly, but I believe it's under the help menu. 

 

ftp://ftp.altera.com/outgoing/release/72_quartus_free.exe 

 

is the web version of Quartus 72. 

 

Pete
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Honored Contributor I
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Re: Your comment "also i tried doing the same file in 7.2 and it gave an error, i made the exact same file, in the morning and it was fine in the lab, i changed the way the pins were named from A[3..0] to A3,A2,A1,A0 and it worked, so i want quartus 2 7.0 because it seems to be better than 7.2".  

 

I guess you are using schematic? Version 7.2 has started doing something more standard with bus naming (to match the standard for VHDL & Verilog etc). If your lab relied on the old MAX+PLUS II way of doing schematic bus naming (like 7.1 and lower), you might see some differences... There's an option to change the behavior back to the old way. I found it in the Help - search for "Instance Naming Rules for Pin Names in the Block Editor".
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Honored Contributor I
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Oh, it'd probably be best if i just stayed with 7.0 since all the notes are based on 7.0. 

 

I asked for a license, it sent me a .dat file in my email, i downloaded it to C:\altera\ and told it where to find the .dat file, and the info showed it would expire in july somewhere and i closed and built the circuit, tried to test it and it refused to compile it or analyse it, so i closed it, googling the message gave no results, so i restarted and tried the trial and then it worked 

 

Edit: oh wait is it the 30 day trial you request? I did get the free version for sure
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