Quartus 2 SignalTap2 LogicAnalyzer Trigger Condition

[Lululukas]

Hello,

Im using  this DE2 Board

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=30

the Project ist added below.

The Design is a Recorder. It saves audio in the sram and plays it back.

I'm currently trying to configure a stp file for the SignalTap analyzer. I can read signals for the keys and the adress_register without problems. But once im adding a trigger, it corrupts the audio. The Audio gets corrupted while recording and while playing the recording, you hear the corrupted version.

Is there something i have to look out, when adding Triggers?

The Screenshot below shows the defined Trigger.

[sstrell]

Any time you add debug logic to a design, you can potentially affect its operation.  You're adding signal stubs which can affect timing.  Does your design meet timing when running a timing analysis?  Does the design function correctly if Signal Tap has not been started?  Or do you have to completely remove it to make the design work correctly?

Also, the KEY signals are commented out in your top level design.  Is that intentional?

And you did not include the .stp file in the .zip.  It's not clear from your screenshot all the signals that are being tapped.  Can you provide the complete list or the .stp?

[Lululukas]

Does the design function correctly if Signal Tap has not been started? Or do you have to completely remove it to make the design work correctly?

• The Design works incorrect bevor SignalTap has been started.
• I have to remove some signals I added to the stp file. Removing the whole file is not necessary.

Also, the KEY signals are commented out in your top level design. Is that intentional?

• That is a Leftover of an older variant. You can the declaration of the KEYs in line 9 of the top level design.

And you did not include the .stp file in the .zip. It's not clear from your screenshot all the signals that are being tapped. Can you provide the complete list or the .stp?

• In the Folder output_files is the stp file "aufgabe5_keys_adress_trigger.stp". Is this not the standart directory for stp files? Quartus put them there by default.

Thank you for your reply.

[ShengN_Intel]

Hi,

Any further update or concern?

Thanks,

Best regards,

Sheng

[Lululukas]

Sadly no update. I've tried to find the error causes by SignalTap in the RTL Viewer.

But no succes so far.

[sstrell]

Signal Tap files are usually placed in the project directory by default since there will not be an output_files directory if the project hasn't been compiled yet.

And now that I've gone into your output_files folder, there is another db and output_files folder in there!  Your project is basically duplicated inside the output_files folder.  I think this needs some cleanup.

And I see four .stp files there.  Which one is causing problems?

Your .sdc file is missing timing constraints for the all the I/O except for the SRAM for some reason.  You need to fully constrain the design and run a timing analysis to verify that the design is meeting timing.  This could very well explain why Signal Tap is affecting functionality.